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CMS-GRPC status

CMS-GRPC status. Imad Laktineh for the GRPC-CMS groups. Motivation. Equip the stations RE1/1, RE2/1, RE3/1 and RE4/1 corresponding to high η region (1.6- 2.4) of the CMS with GRPC using new kind of semi-conductive glass.

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CMS-GRPC status

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  1. CMS-GRPC status Imad Laktineh for the GRPC-CMS groups

  2. Motivation Equip the stations RE1/1, RE2/1, RE3/1 and RE4/1 corresponding to high η region (1.6- 2.4) of the CMS with GRPC using new kind of semi-conductive glass. This allows to improve on trigger efficiency and physics performances.

  3. Single-Gap GRPC Detector R&D Low-resistivity GRPC performance at high rate DESY, January 2012 9 kHz/cm2 is highest rate one can get at DESY

  4. DetectorR&D Multi-Gap GRPC Beam Test@HZDR June, 2012 Time Resolution < 40ps HV scan Rate scan

  5. Electronics R&D CMS-GRPC • Goals • To develop/adapt readout electronics which stands high rate and • allows to exploit the time precision the RPC: •  < 1 ns in case of single-gap GRPC •  < 100 ps in case of multi-gap GRPC

  6. 4.7 mm 4.3mm R&D for single gap and sub-nanosecond time resolution • - Use the 64-channel HARDROC ASICsused to read the GRPC pf the Semi Digital HCAL prototype of ILC • Use appropriate “Link Box” (available) • Use a TDC with better than 100 pstime • Design new PCB with pick-up strips (pitch of 1.5 mm) • on two faces. The PCB is of a square shape (30X30 cm2). ASICs are embedded • on the PCB and only one side is read out. • This can be used to equip the small GRPC already tested • with the same electronics (but without the TDC ) and then use cosmic rays to check the sub-nanosecond time resolution. ASICs : HARDROC 64 channels, SiGe Trigger less mode 3 thresholds Range: 10 fC-15 pC Gain correctionuniformity I2C protocol. Cabling is ongoing

  7. R&D for multi gap and <100 ps time resolution • Use the 16-channel PETIROC ASICs (omega group-Paris) : • High bandwidthpreamp (GBWP> 10 GHz), <3 mW/ch, dual time and charge measurement up to 2500 pe, jitter< 10 psrms • To do list: • Develop a new Link Box • Use a TDC with 25 ps time resolution (available) per ASIC • Design new PCB with pick-up strips (different values of pitch) • ASICs and the Link Box are on the same PCB (on the edge) • the two strip’s ends are read out with two different ASICs • -The final size of the PCB will be that of RE1/X detector. OMEGA, NCEPU, TSINGUHA The aim is to include a TDC in each channel (2014)

  8. 24Ch 25ps TDC module 100M Ethernet Readout with TCP/IP support Cyclone-II FPGA EP2C35F484C6 Socket for TCXO (opt.) Tsinghua university Differential input connector

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