1 / 22

Performances and Prototyping for the Fast Multiplicity implementation

Performances and Prototyping for the Fast Multiplicity implementation. ALICE-PIXEL-Rome F. Meddi, S. Di Liberto , M. A. Mazzoni , G. M. Urciuoli . M. Marini , S. Sestito . G. Astone , M. Spaziani. Summary: [1] Minimum value of #PIXEL vs efficiency:

lara-hull
Télécharger la présentation

Performances and Prototyping for the Fast Multiplicity implementation

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Performances and Prototyping for the Fast Multiplicity implementation ALICE-PIXEL-Rome F. Meddi, S. Di Liberto, M. A. Mazzoni, G. M. Urciuoli. M. Marini, S. Sestito. G. Astone, M. Spaziani. CERN - SPD/ITS Meeting F.Meddi

  2. Summary: [1] Minimum value of #PIXEL vs efficiency: comparison of Fast Multiplicity signal obtained by -single sampling -double sampling - integration [2] Double Integrator prototype for Fast Multiplicity: - realization and measurements time scale [3] DAC’s working point study for Fast-Or - laboratory set-up - single chip measurements strategy CERN - SPD/ITS Meeting F.Meddi

  3. [1] Comments on minimum value of #PIXEL vs efficiency from Fast Multiplicity signal: - data sample taken last September 2002 on the pixel-bus prototype, analyzed in order to choose optimized single and double sampling time(s) and integration time window Pedestal Study: By a digital scope [LeCroy9360-600MHz-5GS/S] N = 136 sweeps Dt = 0.4 ns/sample (20 ns/div & 502 sample) CERN - SPD/ITS Meeting F.Meddi

  4. s(PEDESTAL) vs Time N=136 Dt=0.4ns [mV] 238ns 263ns 288ns < PEDESTAL > vs Time [mV] 263ns 238ns 288ns [s] PEDESTAL: It shows a maximum sampling 50ns after 238ns (i.e. at 288ns) .... It is better sampling 25ns after 238ns (i.e. at 263ns) Confirmed also by a Pedestal’s autocorrelation study. P.S. Times are measured respect to T.P. CERN - SPD/ITS Meeting F.Meddi

  5. 0 100 200 300 ns CLK T.P. F.M. 20ns 30ns 280ns 220ns 320ns CERN - SPD/ITS Meeting F.Meddi

  6. Minimum #PIXEL/BUS obtainaible with Fast Multiplicity: • Asking that: • 1) The Signal (S) could be reduced by 2*s(S) • and • 2) The Pedestal (Ped) could be increased by 2*s(Ped) • (i.e. asking : D2º [S – 2*s(S)] – [Ped + 2*s(Ped)] ³ 0) • 37 ± 2 Pixel/Bus Single sampling @ 263ns • 35 ± 5 “ Integrating in 100ns window • 35 ± 3 “ Double sampling @ 263ns & @ 363ns • …But, the integration method is more reliable respect to the others • because it is more stable respect to real system variability characteristics: • In fact, • variing the integration time of 25ns Þa variation of ~ 15%; • moving of 25ns the sampling time Þa factor of ~ 2 worse; CERN - SPD/ITS Meeting F.Meddi

  7. @238ns (sfit/SLOPE) = 4.9 PIXEL/BUS D2 = 0  (73.3 ± 5.7) PIXEL/BUS @263ns (sfit/SLOPE) = 2.8 PIXEL/BUS D2 = 0  (37.3 ± 2.3) PIXEL/BUS Single-SAMPLING: CERN - SPD/ITS Meeting F.Meddi

  8. “in-time” @238ns “out-time” @338ns (sfit/SLOPE) = 4.4 PIXEL/BUS D2 = 0  (63.7 ± 4.6) PIXEL/BUS “in-time” @263ns “out-time” @363ns (sfit/SLOPE) = 3.0 PIXEL/BUS D2 = 0  (34.6 ± 2.5) PIXEL/BUS DOUBLE-SAMPLING: CERN - SPD/ITS Meeting F.Meddi

  9. Integration in a Time Window of 75ns (sfit/SLOPE) = 1.9 PIXEL/BUS D2 = 0  (41.0 ± 5.2) PIXEL/BUS Integration in a Time Window of 50ns (sfit/SLOPE) = 4.1 PIXEL/BUS D2 = 0  (58.8 ± 6.1) PIXEL/BUS INTEGRATION IN FIXED TIME WINDOW: CERN - SPD/ITS Meeting F.Meddi

  10. Integration in a Time Window of 150ns (sfit/SLOPE) = 3.8 PIXEL/BUS D2 = 0  (30.4 ± 3.0) PIXEL/BUS Integration in a Time Window of 100ns (sfit/SLOPE) = 5.7 PIXEL/BUS D2 = 0  (34.5 ± 4.7) PIXEL/BUS INTEGRATION IN FIXED TIME WINDOW: CERN - SPD/ITS Meeting F.Meddi

  11. EFFICIENCY “e” vs. #FIRED PIXELS on a BUS: e # Fired Pixelsn Signal S & s(S) Pedestal P & s(P) Dkº [S – k*s(S)] – [P + k*s(P)] Dk ³ 0 Þ k£ [(S – P) / (s(S) + s(P))] Þ e (n) = ò Gauss k - ¥ n (#PIXEL/BUS) CERN - SPD/ITS Meeting F.Meddi

  12. +2*s -2*s < (#PIXEL / Half-Stave) > dn / dh Minimum (dn / dh) obtainaible with Fast Multiplicity: In the case of a PIXEL BUS of the inner SPD: a threshold of 35 pixels corresponds to 22 tracks (using a mean C.L. of 1.56)(*) ...tacking into account fluctuations in “f” ß @ ±2*s (dn / dh) ~ 350 (±30%) (*) Thanks to T.Virgili CERN - SPD/ITS Meeting F.Meddi

  13. Control Logic mC (DSP) CLK PC T.P. Double Integrator FIFO A/D F.M. [2] Double Integrator prototype for Fast Multiplicity: - Functional blocks discussed with G. Anelli CERN - SPD/ITS Meeting F.Meddi

  14. CLK Control Logic T.P. SW2 SW3 IFM-Chip IFM-Chip SW4 Microcontroller SW1 ADC FIFO (DSP) SW1 Board SW5 - Double integrator: CERN - SPD/ITS Meeting F.Meddi

  15. CLK T.P. SELECT CH1 SELECT CH2 SW1 FPGA ò SW2 HOLD SW3 ò SW4 HOLD SW5 - Control Logic: CERN - SPD/ITS Meeting F.Meddi

  16. RST GTL/TTL F.O. COUNTER T.P. DISPLAY • [3] Working point study for Fast-Or: • Measurements done on a single chip • (.... tests repeated on several chips required) • Simple h/w added to the Standard Pixel System Test Set-up to count the Fast-Or signals CERN - SPD/ITS Meeting F.Meddi

  17. Fast-Or ERROR Probability: For DAC[20] = 0 ~ 100 ß Fast-Or error probability: Þ Few spurious hits (< 2 10-3 ) @Pre_VTH = 220 (~1200e) Þ“No” spurious hit (i.e. < 10-6 ) @Pre_VTH = 215 (~1600e) (@ PreVTH=220) CERN - SPD/ITS Meeting F.Meddi

  18. L C R C R L Fast-Or pulse efficiency[#FO /#TRG] @ Pre_VTH=215vs DAC[20] value with only 1 fired pixelfar or close the chip “pad area” In the range: DAC[20]=30 ~ 90 ß Fast-Or for 1Fired Pixel (r#2, r#252; c#7, c#15, c#22) Efficiency = 100% Without any spurious hit ( < 4 *10-4 ) CERN - SPD/ITS Meeting F.Meddi

  19. Fast-Or pulse efficiency[#FO /#TRG] @ Pre_VTH=215vs DAC[20] value with 2 fired pixel along column in several zones of the chip matrix (r#2-3, r#252-253; c#7, c#15, c#22) CERN - SPD/ITS Meeting F.Meddi

  20. Fast-Or pulse duration vs DAC[20] value with only 1 fired pixel @ Pre_VTH=215 (r#2, r#252; c#7, c#15, c#22) CERN - SPD/ITS Meeting F.Meddi

  21. On the whole chip: FWHM 17~40 ns jitter18ns max 10ns 4 3 2 1 5 6 2 4 6 1 3 5 Fast-Or pulse duration withonly 1 fired pixel @ (DAC[20] = 60 & Pre_VTH = 215) CERN - SPD/ITS Meeting F.Meddi

  22. Conclusion: [1] Minimum value of #PIXEL vs efficiency obtainable from Fast Multiplicity signal from a single half-stave by integration in 100ns time window: 35 ± 5 [2] Double Integrator prototype for Fast Multiplicity needs to be ready before the submission of FADC chip for functionality feedback check: - prototype realization andmeasurements: end of March [3] DAC’s working point study for Fast-Or: - full efficiency with 1 fired pixel: DAC[20] = 30 ~ 90 @ Pre_VTH=215 - more systematic study: end of April CERN - SPD/ITS Meeting F.Meddi

More Related