Effective Implementation of a 32-bit RISC Processor

1. Effective Implementation of a 32-bit RISC Processor Pirouz Bazargan Sabet University of Paris 6 - LIP6 - ASIM Pirouz.Bazargan-Sabet@lip6.fr

2. Outline Architecture of a RISC Processor Implementation

3. External view Specifications of the processor What the processor is supposed to do Introduction Architecture ? All aspects visible from the USER’s (programmer) point of view

4. Internal view How much time does it take to perform some operation ? Which hardware may be used and how it should be organized to make the specifications feasable Introduction Implementation ? All aspects visible from the DESIGNER’s point of view

5. Software visible registers Memory Addressing The instruction set The exception / reset mechanism Architecture

6. Architecture Architecture of the MIPS processor Mips ? A 32-bit processor One of the two first RISC architectures Defined in 1981 by the Architecture ResearchGroup at the Stanford University (John Hennessy)

7. Architecture Simplified Mips-R3000 architecture No floating point operations No virtual memory management

8. Software visible registers MemoryAddressing The instruction set The exception / reset mechanism Architecture

9. Architecture Software visible registers Registers that can be manipulated (written and read) in the assembly language

10. Software Visible Registers 32 common 32-bit registers Integer Registers R0 …. R31 Addressed from their number

11. R31 : The Link Register When a subroutine is called, the return address is saved into R31 Software Visible Registers R0 : The Trash Register R0 contains always 0 A value written into R0 is lost

12. HI 32 most significant bits Multiply LO 32 least significant bits HI Result Divide LO Remainder Software Visible Registers Two 32-bit registers : HI and LO Used by multiply and divide instructions

13. SR Status Register CAUSE Cause Register (cause of exceptions) EPC Exception Program Counter (return address in case of exception) BAR Bad Address Register (illegal memory address) Software Visible Registers Four 32-bit special registers : Coprocessor Registers Needed to implement an operating system

14. Software visible registers Memory Addressing The instruction set The exception / reset mechanism Architecture

15. Read / Write operations 3 types of data : Byte Half-word (2 bytes) Word (4 bytes) Memory Addressing 32-bit address a 4 Gbytes of memory space

16. The current mode is defined by the Status Register 1 Status Register 1 : user 0 : kernel Memory Addressing The processor can operate under 2 modes User / Kernel

17. Memory Addressing 0000 0000 The memory space is divided into 2 parts USER 7FFF FFFF 8000 0000 In User mode the processor can only access the addresses ranged from 0000 0000 to 7FFF FFF FFFF FFFF

18. The frontier protects the OS Memory Addressing 0000 0000 The OS protects the hardware against an error in a User program USER 7FFF FFFF 8000 0000 O S FFFF FFFF

19. Memory Addressing Data alignment rule Msb lsb register memory

20. Memory Addressing Bytes’ order : Little Endian 0000 0000 Msb lsb register FFFF FFFF memory

21. a multiple of 4 Address of a Word a multiple of 2 Address of a Half-Word a multiple of 1 Address of a Byte Memory Addressing Address alignment rule The address of an object of N bytes must be multiple of N

22. Architecture Software visible registers Memory Addressing The instruction set The exception / reset mechanism

23. All instructions have the same size (32 bits) 3-operand instructions (2 read, 1 write) No operation involving operands in memory - Only load and store operations Instruction Set RISC Architecture Only simple instructions

24. Instruction Set 3 instruction formats R Register-register instructions I Immediate instructions J Jump instructions

25. 6 5 5 5 5 6 opcod rs rt rd sham func opcod Operation code func Function (opcod extension) rs # of source register rt # of source register rd # of destination register sham Shift amount (# of bit the opr. is shifted) Instruction Set R format

26. 6 5 5 16 opcod rs rt/rd imd opcod Operation code rs # of source register rt / rd # of source or destination register imd Immediate value Instruction Set I format

27. 6 26 opcod imd opcod Operation code imd Immediate value Instruction Set J format

28. Instruction Set Arithmetic and logic instructions Memory access instructions Control instructions System instructions

29. opcod rs rt rd func R format Arithmetic and logic Assembly language Format Action Add Rd, Rs, Rt Rs+Rt a Rd Overflow a exc. add

30. opcod rs rd imd I format Rs Imd Rd Arithmetic and logic Assembly language Format Action Addi Rd, Rs, Imd Rs+Imd a Rd add immediate Overflow a exc. Imd is sign extended

31. Arithmetic and logic Assembly language Format Action Addu Rd, Rs, Rt Rs+Rt a Rd opcod rs rt rd func add unsigned No overflow R format

32. Arithmetic and logic Assembly language Format Action Addiu Rd, Rs, Imd Rs+Imd a Rd opcod rs rd imd add immediate unsigned Imd is sign extended No overflow I format Rs Imd Rd

33. Arithmetic and logic Assembly language Format Action Rs–Rt a Rd Sub Rd, Rs, Rt opcod rs rt rd func Overflow a exc. subtract R format

34. Arithmetic and logic Assembly language Format Action Rs–Rt a Rd Subu Rd, Rs, Rt opcod rs rt rd func Subtract unsigned No overflow R format

35. Arithmetic and logic Assembly language Format Action Or Rd, Rs, Rt Rs or Rt a Rd opcod rs rt rd func bitwise logic OR R format

36. Rs Imd 0 0 0 0 Rd Arithmetic and logic Assembly language Format Action Ori Rd, Rs, Imd Rs or Imd a Rd opcod rs rd imd bitwise logic OR immediate Imd is zero extended I format

37. Arithmetic and logic Assembly language Format Action And Rd, Rs, Rt Rs and Rt a Rd opcod rs rt rd func bitwise logic AND R format

38. Arithmetic and logic Assembly language Format Action Andi Rd, Rs, Imd Rs and Imd a Rd opcod rs rd imd bitwise logic AND immediate Imd is zero extended I format Rs Imd 0 0 0 0 Rd

39. Arithmetic and logic Assembly language Format Action Xor Rd, Rs, Rt Rs xor Rt a Rd opcod rs rt rd func bitwise logic XOR R format

40. Arithmetic and logic Assembly language Format Action Xori Rd, Rs, Imd Rs xor Imd a Rd opcod rs rd imd bitwise logic XOR immediate Imd is zero extended I format Rs Imd 0 0 0 0 Rd

41. Arithmetic and logic Assembly language Format Action Nor Rd, Rs, Rt Rs nor Rt a Rd opcod rs rt rd func bitwise logic NOR R format

42. Rt Rd 0 Sham Arithmetic and logic Assembly language Format Action Sll Rd, Rt, Sham Rt << Sham a Rd opcod rt rd sham func Shift left logic R format

43. Arithmetic and logic Assembly language Format Action Sllv Rd, Rt, Rs Rt << Rs a Rd opcod rs rt rd func Shift left logic variable R format Rt Rd 0 Rs Only the 5 lsb of Rs are meaningful

44. Rt Rd 0 Sham Arithmetic and logic Assembly language Format Action Srl Rd, Rt, Sham Rt >> Sham a Rd opcod rt rd sham func Shift right logic R format

45. Arithmetic and logic Assembly language Format Action Srlv Rd, Rt, Rs Rt >> Rs a Rd opcod rs rt rd func Shift right logic variable R format Rt Rd 0 Rs Only the 5 lsb of Rs are meaningful

46. Rt Rd Arithmetic and logic Assembly language Format Action Sra Rd, Rt, Sham Rt >> Sham a Rd opcod rt rd sham func Shift right arithmetic R format Sham

47. Arithmetic and logic Assembly language Format Action Srav Rd, Rt, Rs Rt >> Rs a Rd opcod rs rt rd func Shift right arithmetic variable R format Rt Rd Rs Only the 5 lsb of Rs are meaningful

48. Arithmetic and logic Assembly language Format Action Slt Rd, Rs, Rt Rs < Rt ? opcod rs rt rd func Yes : 1 a Rd Set if less than R format No : 0 a Rd Operands are signed

49. Arithmetic and logic Assembly language Format Action Slti Rd, Rs, Imd Rs < Imd ? opcod rs rd imd Yes : 1 a Rd Set if less than immediate I format No : 0 a Rd Operands are signed Imd is sign extended

50. Arithmetic and logic Assembly language Format Action Sltu Rd, Rs, Rt Rs < Rt ? opcod rs rt rd func Yes : 1 a Rd Set if less than unsigned R format No : 0 a Rd Operands are unsigned