1 / 4

PIDS Key Issues

2004 ITWG Meeting Stresa, Italy April 20, 2004. PIDS Key Issues. Peter M. Zeitzoff US Chair. Participants: this ITWG. Liko Beldi (ST Microelectronics) Simon Deleonibus (LETI) Guillermo Bomchil (ST Microelectronics) Jan-Erik Muller (Infineon) Stefaan Deisuter (IMEC)

lawson
Télécharger la présentation

PIDS Key Issues

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. 2004 ITWG Meeting Stresa, Italy April 20, 2004 PIDS Key Issues Peter M. Zeitzoff US Chair

  2. Participants: this ITWG • Liko Beldi (ST Microelectronics) • Simon Deleonibus (LETI) • Guillermo Bomchil (ST Microelectronics) • Jan-Erik Muller (Infineon) • Stefaan Deisuter (IMEC) • Kristin DeMeyer (IMEC) • George Bourianoff (Intel) • Ingmar Meijer (IBM) • Toshihiro Sugii (Fujitsu) • Yasuo Inoue (Renesas Technology) • Toshiro Hiramoto (Univ. of Tokyo) • Shinichi Takagi (Univ. of Tokyo) • Jim Hutchby (SRC) • Joe Brewer (Univ. of Florida) • Lalita Manchanda (SRC) • Kang Wang (UCLA) • Ming-Jinn Tsai (ITRI)

  3. 2004 update: no major changes anticipated updates and corrections DRAM half pitch: ’03 ITRS projection of 90 nm in 2004 appears likely 2005 ITRS CD control of Lg: proposed increase in maximum 3-sigma variation from 10% to 12% This is an inter-TWG and chip size study group issue: no decision yet PIDS will support other TWGs, especially Design Impact of the proposed increase on transistor characteristics, esp. Vt statisticalvariation Modeling and Simulation TWG may be able to help Scaling of feature size to be re-evaluated for both DRAM and flash Is flash scaling catching up with, surpassing DRAM scaling? Key PIDS Issues

  4. 2005 issues (con’t.) Logic: scaling goals, models, and results to be reviewed, updated Maximum leakage current requirements, particularly for low-power logic With Design TWG: evaluate scaling of power dissipation and related issues Improved models: capacitance, poly depletion and inversion layer effects, enhancements from advanced devices, etc. Timeline of potential solutions NVM: considering transfer of phase change and floating body memory from ERD section to PIDS tables Key PIDS Issues (continued)

More Related