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D0 Trigger Status

D0 Trigger Status. 7 MHz input rate Data. Brief discussion of each project Great progress all systems Significant delays Manpower Shortages Technical Difficulties Delivery. Framework. Data Log. L1 4.2 m s. L2 100 m s. L3 48+ ms. 50 Hz. 7 kHz.

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D0 Trigger Status

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  1. D0 Trigger Status 7 MHz input rate Data • Brief discussion of each project • Great progress all systems • Significant delays • Manpower Shortages • Technical Difficulties • Delivery Framework Data Log L1 4.2 ms L2 100ms L3 48+ms 50 Hz 7 kHz 1000 Hz 48 nodes 128 terms 128 terms

  2. Framework Status • Components(MSU) • Operational • Commissioning/Schedule • Support detector commissioning • Complete readout to L3 by 1/11 • Integrating with L2 • L2 trigger mask and pseudo-terms deferred? • Firmware • Need to complete pseudo-terms • Commission run-control • Personnel • Loss of senior engineer, Steve Gross • Loss of engineer, Kirsten Moore • Replacement uncertain Good progress, on time

  3. L1CAL Detector/L1/L2 Components L1 LUM LUM L2Cal CAL L1 FPS FPS L2PS CFT/ CPS Global L2 L1 CTP L2CFT L2STT SMT L2 Muon L1 Muon Muon L2FW:Combined objects (e, m, j) L1FPD FPD L1FW: towers, tracks, correlations

  4. Luminosity Monitor Status • Components(Brown) • Scintillator(48) Complete • Electronics • CAFÉ boards(175) on hand • Completing ADC(~12) board layout, ordering parts • Vertex board, FPGA 75% complete, layout commencing. • Procuring signal cables(~60) soon • Crate/PS on hand • Commissioning/Schedule • Installed Scintillator 4/00 • Cabling awaits FPS. • February 1, Electronics Installed • March 1, Luminosity Monitoring • March-April, and/or terms. • Software • Working on embedded software • Download currently underway. • Database under development Good progress, on time

  5. CTT Organization showing links to the L1 TM, L2 PreProcessors and L3 AFE MIX DB/DBTC COL BC TM L3 OCT 1 CFT L1CFT Ax. /CPS Ax. L3 75 L3 OCT 2 L3 OCT 3 L2CFT · Q 1 L3 L2PS OCT 4 L2CFT · Q 2 L3 L2PS OCT 5 L2CFT Q 3 · 40 L3 L2PS OCT 6 L2CFT · Q 4 L3 · L2PS OCT 7 CPS · L3 Ax. · m OCT 8 L1 TM 5 OLR 1 L2STT SEXT 1 L3 OLR 2 L2STT SEXT 2 L3 OLR 3 L2STT SEXT 3 L3 OLR 4 L2STT SEXT 4 L3 OLR 5 L2STT SEXT 5 L3 CFT OLR 6 Stereo. L2STT SEXT 6 75 L3 L2PS N U L3 5 L2PS N V L3 CPS L2PS Stereo S U L3 10 L2PS S V L3 L2FPS N U L3 L2FPS N V L3 FPS L1FPS 16 L3 L2FPS 32 S U L3 L2FPS S V L3 LEGEND Analog Boards FSC LINK LVDS LINK the inset shows CFT LVDS LINK the number of G LINK Stereo. each type 3 TRANSITION CARDS DAUGHTER CARDS Each color Each filling corresponds to a corresponds to a Created by Manuel I. Martin different flavor different flavor May. 6, 99 L1CTP/FPS/FPD

  6. L1 CTP/FPS/FPD Status • Components • Analog(Fermilab-D0) • AFE-8MCM (CFTax): At vendor, full order complete 1/18/00 • AFE-12MCM (FPS): • motherboard prototype this month • daughter prototype board order 1/01 • Crates/Cables on hand • Power supplies delayed until new year (partial). • Mixer(Fermilab-CD) • Super-sector (1/5th) 11/15 • Full Mixer 1/01 • Digital(Fermilab-D0) • Motherboard here • Transition module 1/11 • CTP daughter boards 11/15 • FPS daughter board order out, parts on order • Crates/Cables/PS here • Firmware • AFE & Mixer complete • DFE 50% • Collector/Broadcaster 50% • No diagnostics

  7. L1 CTP/FPS/FPD Status • Commissioning/Schedule • Assembling test stands for digital/VHDL • Installing cables/crates on platform • Crates/Cables installed in MCH. • Analog • 10 AFE8 installed, operating 12/00 • Balance at FNAL by 1/18/01 • AFE12 unknown (in prototype) • Supplies as arrive • Digital • Sufficient hardware for commissioning • Balance Installed by 12/00 • Personnel • Recently lost Kin Yip (FNAL postdoc) & Juan Lizarazo (FNAL Co-op) both on VHDL • A position has been available but not yet filled & a new student arrived. • Reduced engineering (John Anderson) has delayed AFE12. • Have redirected Jamieson Olsen to assist with VHDL, Fermilab arranging technical help to assist reorganization and installation. Good progress on all fronts AFE12, VHDL concerns

  8. L1 CAL Status • Components • Analog pick-offs (320) to accommodate changed BW prototyped. 1FTE month to production • Quadrant hardware (40) circuit/firmware designed • L2/L3 Readout complete • Commissioning/Schedule • Inactive until framework complete 11/00. Within a month progress should resume • Start w/ analog pick-offs • L2 & L3 readout 11/00 • Firmware • All exists, not all tested • Personnel • Same as framework Late but well before 3/01

  9. L1 MUON Status • Components • L1MuTrigger (4 crates) Prod Beginning(UAz) • Motherboard: starting production/fabrication • Scintillator daughter board: preproduction in assembly • Wire daughter board: production board in design • Crate Manager: testing production card, balance to be assembled • Trigger Manager daughter-board: starting prod/fab now • Serial Link Transmitters complete • Serial Link Receivers production testing • MCEN (5 crates) in Preprod Testing(BU) • MCEN: preproduction testing underway • Centroid Daughter Board: preprod, testing underway • Crate manager: preprod layout. • Crates/Backplanes complete • Power Supplies on order.

  10. L1 Muon Status • Software • Download Infrastructure in place • Preproduction versions of all firmware exist. • No alarms, monitoring • Personnel • Arizona down to zero from two postdocs. Advertising for one replacement • Boston post doc hired, visa difficulties • Discussing Ken Johns buy-out. • Need help w/ assembly/test of PSupplies • Commissioning/Schedule • One trigger, one manager crate in operation and readout. • Next providing L1CTPT Manager Crate. • Two Octants triggering by 11/00 • L1 Muon full crate assembled 1/01 • MCEN full crate assembled 3/01 L1Muon before 3/01 Some concern MCEN, manpower

  11. L2 Component Status • Alpha serial processors (MSU,UM,UIC): • Production Status • 3 preproduction worked “out-of-the-box” • ADCO, same vendor that produced CDF TDCs • About 25 stuffed or nearly stuffed • Parts for another 15 in reserve • Many key components obsolete • Diagnostics @ UM • Four boards • To our knowledge none work • Diagnostics @ UIC • 10 boards • 2 incorrectly mounted components 8 have partial functionality • Rapid learning curve • Considering a range of options • Repair sufficient boards for March 1, 2001 • Build new boards with larger vias and reserve parts • Build new boards with larger vias. Recover components and build full complement. • Re-layout board and/or find new vendor • Complete redesign • Hope to decide before November 1, leaning towards full press: repair, new boards, and redesign • Complicating commissioning.

  12. L2 Components Cont. • MBT I/O Cards(U-Maryland): • 6 production cards received. 3 pass specs. 3 under test now • Firmware functionality 90% done. • Remaining 25 boards built, parts on hand • Balance by December. • FIC L1/L2 Interface(SACLAY): • Boards complete • Final firmware adjustments October 16-20. • SLIC Parallel Proc.(NIU,Columbia): • Boards complete • First results from DSP Central algorithm meet speed/efficiency requirements • CIC, SFO Muon/L2 Interface (U-Neb): • Prototypes pass battery of tests but not up to standard design practices (two layers, unconventional shielding planes, unequal traces on differential signals...) • Have solicited advice from Fermilab engineers but process delayed by illness. Restarting now. • Delivery December?

  13. L2 Status Cont. • Software • C++ Framework exists • Preprocessor algorithms well developed, global needs attention. • Commissioning/Testing: • MCH and test stand racks and crates 85% done. Cabling 65% done • Commissioning sequence under discussion. • Essentially on hold until alpha, CIC, SFO issues resolved. • Once alpha’s MBTs are on hand the L2CAL, L2CTT, L2PS can be assembled <1 month. • Personnel • Recently lost one key postdoc from UIC and one from Maryland, will lose another UIC postdoc at the end of the year • One UIC postdoc has been replaced and new ones added from MSU and Columbia • Lack of on-site coordinator has slowed progress. Discussing Nikos Varelas buy-out. • Lack of project engineer has slowed progress. However, Rich Kwarciany (CD Electronics System Engineer) has been a great help as an on-call consultant. Fermilab looking into this. MBT, SLIC, FIC ready before 3/01 Alpha, CIC/SFO, manpower concerns

  14. STT • Motherboard & communication daughter board • First prototypes in hand or being built • November • Fiber Road & Track Fit daughter boards • Parts in hand • prototypes coming (Feb/ Dec) • VHDL and simulation in progress • STC(hit filter, cluster finder) • VHDL design/coding in progress • Not easy to fit into real estate • May change Altera to Xilinx? • Or fancier Altera? • VME CPU: purchase in progress • Schedule • Schedule in mid-update • Attempt integration in Feb 2001 with first prototypes, not 2nd • Scheduled Complete Feb 2002

  15. Digitizing Crates (2 of 16 groups) Data pathway o o o Receiver Collector (1 of 8) o o o VBDs Fiber Path (8 total) Event Tag Generator Levels 1,2 Trigger data o o o o o o Event tag path o o o o o o Segment Bridge Processor Nodes (4 groups of 16) DAQ/L3 • Evolved to a single multipurpose card used in VRC, SB, processor nodes (~100) • VHDL code specific to VRC, SB, Node complete • ETG is one of a kind.

  16. L3/DAQ Status • Components(Brown) • Layout done for 6 wks, parts procurement difficult. • 25 board order placed with vendor • Layout @ board houses. Bids received. Production complete < 2 weeks. • Procuring parts now w/ Fermilab assistance • 5 days to stuff & check • Software(Brown,Washington) • Framework up and running • Nodes also operational • Commissioning/Installation • Maintaining emulators for commissioning, no schedule delay for other systems. • Cable plant is minimal - reuses infrastructure, MCH 50% done, remainder under discussion. • Schedule (full chain by Jan 1) • After receipt of board 1-2 week at Brown, then install 4 VRCs @ DAB • 2 wks install 1 SB, fiber between VRC-SB • 2 wks install multiple node adapters, fiber between SB-node. • ETG January Software in good shape Watching delivery closely

  17. Filtering/Database • Components(Various Institutions) • Operational version of ScriptRunner • Unpacking code for cal, smt and muon • electron, muon, jet, missing et, and tau tools • Database and interface in design. • Installation/Commissioning • Participating in online tests of PDTs, CFT. • Participating in 10% SiDet Test • Milestone: readout/filtering muon system! • Personnel • Impending departure of Charles Leggett (LBL) infra-structure (unpack,tool template,offline verification) • Carmem Silva (LAFEX) database, currently only 1FTE on database • Insufficient support for NT release & porting. • Too few tool authors! • Schedule • 11/00 standard running including ScriptRunner in Mark & Pass mode • 1/01 monitor displays available • 3/01 operational versions of all physics tools ported and available Filtering operable, needs personpower

  18. Reportable Milestones Priorities: (1) FWK, L1mu, L1CAL, L3 (2) L2Global, L2CAL (3) L1&L2 CTPT, FPS

  19. Personnel Increases? • To free engineers for VHDL preparation a senior technician to assist CTPT construction. Could also help with L1Muon, L2 installation. Fermilab investigating. • An engineer to assist L2 debugging & integration. This could be considered an escalation of the already valuable on-call arrangement. Fermilab investigating • Trying to arrange full-time contributions from • Ken Johns L1Muon • Nikos Varelas L2 • Looking fortwo programmers for • L3 infrastructure/release (Fermilab/LBL?) • Database (Collaboration?) • Other needs: • Examines • L2 tools & verification • L3 tools & verification!

  20. Closing Comments • Trigger making excellent progress in all areas. (Didn’t mention TrigSim but will be a release Nov 1.) • Responding to delays by adding people to construction and commissioning efforts. • Will make L2alpha decision soon & trying to accelerate L3 component delivery. • First priority FMWK, L1CAL, L1Muon, L3. Then will add systems as components come available. • Now’s the time to help: tools, filtering, database, commissioning.

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