CSET 4650 Field Programmable Logic Devices

Introduction to CMOS Complementary Metal-Oxide Semiconductor CSET 4650 Field Programmable Logic Devices Dan Solarek

CMOS Technology • Complementary MOS, or CMOS, needs both PMOS and NMOS FET devices for their logic gates to be realized • The concept of CMOS was introduced in 1963 by Frank Wanlass and Chi-Tang Sah of Fairchild • did not become common until the 1980’s as NMOS microprocessors were dissipating as much as 50W and alternative design techniques were needed • CMOS still dominates digital IC design today

MOSFET Transistors • Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are the transistors most widely used in integrated circuits today • The name is due to: • the structure of the device - a sandwich of a metal conductor, an oxide insulator, and a semiconductor substrate • the way it works - an electric field controls the flow of current through the device • Although early MOSFET transistors used metal for the first layer, current ones use a polysilicon material • a conductive material with somewhat more resistance than a normal conductor and is easier to fabricate

N-Channel MOSFET Transistors • With no voltage between the gate terminal and the substrate, there are two junctions between the two N regions and the P region. • This acts like two oppositely connected diodes, and no current can flow between source and drain.

N-Channel MOSFET Transistors • Application of a positive voltage between the gate terminal and the substrate creates an electric field that drives holes out of the region under the gate, creating a channel of N-type material that connects the source and drain terminals • Current is due to electron movement in the N-channel

P-Channel MOSFIT Transistors • The P and N regions are reversed from the N-Channel device. • Application of a voltage on the gate terminal that is negative relative to the substrate creates a P channel beneath the gate and charge flow is due to hole movement.

MOSFET Circuit Symbols • The following symbols are used to represent MOSFET transistors in circuit diagrams: normally on normally off

MOSFET Circuit Symbols • The following simplified symbols are used to represent MOSFET transistors in most CMOS circuit diagrams: negative voltage

MOSFET Circuit Symbols • The gate of a MOS transistor controls the flow of the current between the drain and the source. • The MOS transistor can be viewed as a simple ON/OFF switch.

nMOS pMOS MOSFET Circuit Symbols • Series behavior of MOS transistors nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON

nMOS pMOS MOSFET Circuit Symbols • Parallel behavior of MOS transistors • nMOS: 1 = ON • pMOS: 0 = ON • Parallel: • either can be ON

Complementary MOSFETS (CMOS) • N-Channel and P-Channel transistors can be fabricated on the same substrate as shown below

CMOS Logic Families

CMOS Logic Families • 74-series (commercial) parts are designed for temperatures between 0°C and 70°C • 54-series (military) parts are designed for operation between -55°C and 125°C • the ’00 NAND gate is the smallest logic-design building block in each family • the ‘138 is a MSI part (~15 NAND gates)

CMOS Logic Families • These specs assume that the 5 Volt supply has a ±10% margin; that is, VCC can be anywhere between 4.5 and 5.5 V.

CMOS Logic Families • Specifications for TTL-compatible CMOS outputs have two sets of output parameters; only one set is used depending on how an output is loaded.

CMOS Logic Families • A CMOS load is one that requires the output to sink and source very little DC current • 20 µA for HC/HCT • 50 µA for VHC/VHCT • A TTL load can consume much more sink and source current • up to 4 mA from and HC/HCT output • 8 mA from a VHC/VHCT output • CMOS outputs maintain an output voltage within 0.1V of the supply rails, 0 and VCC. • a worst-case VCC=4.5V is used for the table; hence, VOHminC=4.4V

Comparison of Logic Levels • (a) 5-V CMOS; (b) 5-V TTL, including 5-V TTL-compatible CMOS; (c) 3.3-V LVTTL; (d) 2.5-V CMOS; (e) 1.8-V CMOS

Properties of NMOS and CMOS Logic Gates • No current flows through the gate unless the input signal is changing • High input impedance • High fan-out • Sandwich structure of MOS transistor creates capacitor between the gate and substrate • High input capacitance • Slows transition time • Limits fan-out or switching speed • NMOS dissipates power in low output state • CMOS gate only dissipates power when it is changing state • The faster a CMOS gate switches the more power it dissipates, so there is a tradeoff between speed and power

Why CMOS is Better • Low DC Power Consumption • Abrupt & well defined Voltage transfer Characteristic • Noise Immunity due to Low impedance between logic levels and Supply/Gnd. • Symmetry between Tfall & Trise • High Density: Si real estate → Yield → Cost • Highly Integrated → Active & High input Impedance → Composition equality • No real trade off between the above

Static vs Dynamic CMOS Design • Static • Each gate output have a low resistive path to either VDD or GND • Dynamic • Relies on storage of signal the value in a capacitance • requires high impedance nodes We will only worry about static design today.

NMOS Logic • Negative charge carriers (electrons) • Positive biasing voltage at gate

CMOS Logic • Transistors come in complementary pairs

Vdd PMOS in out in out NMOS CMOS Inverter • CMOS gates are built around the technology of the basic CMOS inverter: Symbol Circuit

Vdd s g PMOS d out in d NMOS g s Basic CMOS Logic Technology • Based on the fundamental inverter circuit at right • Transistors (two) are enhancement mode MOSFETs • N-Channel with its source grounded • P-Channel with its source connected to +V • Input: gates connected together • Output: drains connected

Charge Open CMOS Inverter - Operation When input A is grounded (logic 0), the N-Channel MOSFET is unbiased, and therefore has no channel enhanced within itself. It is an open circuit, and therefore leaves the output line disconnected from ground. At the same time, the P-Channel MOSFET is forward biased, so it has a channel enhanced within itself, connecting the output line to the +VDD supply. This pulls the output up to +VDD (logic 1). VDD A

VDD Open Out Discharge CMOS Inverter - Operation When input A is at +VDD (logic 1), the P-channel MOSFET is off and the N-channel MOSFET is on, thus pulling the output down to ground (logic 0). Thus, this circuit correctly performs logic inversion, and at the same time provides active pull-up and pull-down, according to the output state. VDD A

CMOS Inverter - Operation Vout Since the gate is essentially an open circuit it draws no current, and the output voltage will be equal to either ground or to the power supply voltage, depending on which transistor is conducting. VDD Vin VDD indeterminant range

CMOS Inverter – A Switch Model • Circuit schematic for a CMOS inverter • Simplified operation model with a high input applied • Simplified operation model with a low input applied

Static Characteristics of the CMOS Inverter – Switch Model • The figure shows the two modes of static operation with the circuit and simplified models • Logic 1 (a) and (b) • Logic 0 (c) and (d) • Notice that VH = 5V and VL = 0V, and that ID = 0A which means that there is no static power dissipation

CMOS Inverter Operation Summarizing: • When vI is pulled high (VDD), the PMOS inverter is turned off, while the NMOS is turned on pulling the output down to GND • When vI is pulled low (GND), the NMOS inverter is turned off, while the PMOS is turned on pulling the output up to VDD

Propagation Delay Estimate • The two modes of capacitive discharging and charging that contribute to propagation delay

Fan-Out in CMOS Circuits • While the fan-out of CMOS gates is affected by current limits, the fan-out of CMOS gates driving CMOS gates is enormous since the input currents of CMOS gates is very low. • Why are the input currents low? • On the other hand the high capacitance of CMOS gate inputs means that the capacitive load on a gate driving CMOS gates increases with fan-out. • This increased capacitance limits switching speeds and is a far more significant limit on the maximum fan-out.

Complementary CMOS • Complementary CMOS logic gates • pMOS pull-up network • nMOS pull-down network • a.k.a. static CMOS

PUN PDN Complementary CMOS • To build a logic gate we need to build two switch networks:

Conduction Complement • Complementary CMOS gates always produce 0 or 1 • Ex: NAND gate • Series nMOS: Y=0 when both inputs are 1 • Thus Y=1 when either input is 0 • Requires parallel pMOS • Rule of Conduction Complements • Pull-up network is complement of pull-down • parallel → series, series → parallel

CMOS Gate Design • Work out the values for both the push and pull networks • Compare them • What is the result?

CMOS Gate Design • A 2-input CMOS NAND gate

CMOS Gate Design • Work out the values for both the push and pull networks • Compare them • What is the result?

CMOS Gate Design • A 2-input CMOS NOR gate

CMOS Gate Design • A 4-input CMOS NOR gate

NAND and NOR are Popular • Logical inversion comes free • as a result an inverting gate needs smaller number of transistors compared to the non-inverting one • In CMOS (and in most other logic families) • the simples gates are inverters • the next simplest are NAND and NOR gates

Compound Gates • Lets take a look at a gate that implements a more complex function …

Compound Gates • Compound gates can do any inverting function • Ex: + · · Y A B C D =

Y = ( A + B + C) D Example: O3AI

CSET 4650 Field Programmable Logic Devices