Digital Integrated Circuits A Design Perspective

1. Digital Integrated CircuitsA Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic DesignMethodologies December 10, 2002

2. The Design Productivity Challenge Logic Transistors per Chip (K) 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 A growing gap between design complexity and design productivity Source: sematech97

3. A Simple Processor MEMORY INPUT/OUTPUT CONTROL DATAPATH

4. A System-on-a-Chip: Example Courtesy: Philips

5. Impact of Implementation Choices 100-1000 Domain-specific processor (e.g. DSP) 10-100 Embedded microprocessor Energy Efficiency (in MOPS/mW) 1-10 Hardwired custom Configurable/Parameterizable 0.1-1 Somewhat flexible Flexibility(or application scope) Fully flexible None

6. Design Methodology • Design process traverses iteratively between three abstractions: behavior, structure, and geometry • More and more automation for each of these steps

7. Y Chart

8. Digital Circuit Implementation Approaches Custom Semicustom Cell-based Array-based Standard Cells Pre-diffused Pre-wired Ma cro Cells Compiled Cells (Gate Arrays) (FPGA's) Implementation Choices

9. The Custom Approach Intel 4004 Courtesy Intel

10. Intel 4004 (‘71) Intel 8080 Intel 8085 Intel 8486 Intel 8286 Transition to Automation and Regular Structures Courtesy Intel

11. Cell-based Design (or standard cells) Routing channel requirements are reduced by presence of more interconnect layers

12. Standard Cell — Example [Brodersen92]

13. Standard Cell – The New Generation Cell-structure hidden underinterconnect layers

14. Standard Cell - Example 3-input NAND cell (from ST Microelectronics): C = Load capacitance T = input rise/fall time

15. Automatic Cell Generation Initial transistor geometries Placedtransistors Routedcell Compactedcell Finished cell Courtesy Acadabra

16. Product terms x x 0 1 x 2 AND OR plane plane f f 0 1 x x x 0 1 2 A Historical Perspective: the PLA

17. Two-Level Logic Every logic function can beexpressed in sum-of-productsformat (AND-OR) minterm Inverting format (NOR-NOR) more effective

18. Or-Plane And-Plane V f GND DD PLA Layout – Exploiting Regularity

19. Breathing Some New Life in PLAs River PLAs • A cascade of multiple-outputPLAs. • Adjacent PLAs are connected via river routing. • No placement and routing needed. • Output buffers and the input buffers of the next stage are shared. Courtesy B. Brayton

20. Experimental Results Area: RPLAs (2 layers) 1.23 SCs (3 layers) - 1.00, NPLAs (4 layers) 1.31 Delay RPLAs 1.04 SCs 1.00 NPLAs 1.09 Synthesis time: for RPLA , synthesis time equals design time; SCs and NPLAs still need P&R. Also: RPLAs are regular and predictable Layout of C2670 Standard cell, 2 layers channel routing Standard cell, 3 layers OTC Network of PLAs, 4 layers OTC River PLA, 2 layers no additional routing

21. MacroModules 25632 (or 8192 bit) SRAM Generated by hard-macro module generator

22. Macromodules • Hard macro examples are multipliers and memories • Soft macros have given functionality, but no physical info. • A-priori timing data not available. • Can be ported over technologies. • Brought about the idea of IP’s.

23. “Soft” MacroModules Synopsys DesignCompiler

24. “Intellectual Property” A Protocol Processor for Wireless

25. IP Examples • Embedded microprocessors and microcontrollers • DSP processors • Bus interfaces (PCI, etc.) • Special purpose functional modules (FFT, filters, etc.) • Error correction coders • MPEG encoders and decoders. • Many others.

26. Design Capture Behavioral HDL Pre-Layout Simulation Structural Logic Synthesis Floorplanning Post-Layout Simulation Placement Physical Circuit Extraction Routing Tape-out Semicustom Design Flow Design Iteration

27. Design Flow Steps • Design Capture: VHDL, Verilog, SystemC, etc. • Logic Synthesis: Synthesis and insertion of macros. • Prelayout simulation and verification: Based on estimated parasitics. • Floorplanning: Based on estimated module sizes. Global power and clock distribution.

28. More General Design Flow

29. RTL Synthesis Flow

30. Standard Cell Place and Route

31. Timing Driven Placement

32. The “Design Closure” Problem Iterative Removal of Timing Violations (white lines) Courtesy Synopsys

33. Integrating Synthesis with Physical Design RTL (Timing) Constraints Physical Synthesis Macromodules Fixed netlists Netlist with Place-and-Route Info Place-and-RouteOptimization Artwork

34. Mixed-Signal Design Flow

35. Array-based Pre-diffused Pre-wired (Gate Arrays) (FPGA's) Late-Binding Implementation

36. Gate Array — Sea-of-gates

37. Sea-of-gate Primitive Cells

38. Example: Base Cell of Gate-Isolated GA From Smith97

39. Example: Flip-Flop in Gate-Isolated GA From Smith97

40. Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6 mm CMOS) Courtesy LSI Logic

41. The return of gate arrays? Via programmable gate array(VPGA) Via-programmable cross-point metal-6 metal-5 programmable via Exploits regularity of interconnect [Pileggi02]

42. Prewired Arrays Classification of prewired arrays (or field-programmable devices): • Based on Programming Technique • Fuse-based (program-once) • Non-volatile EPROM based • RAM based • Programmable Logic Style • Array-Based • Look-up Table • Programmable Interconnect Style • Channel-routing • Mesh networks

43. Fuse-Based FPGA antifuse polysilicon ONO dielectric n antifuse diffusion + 2 l Open by default, closed by applying current pulse From Smith97

44. I I I I I I 5 4 3 2 1 0 Programmable I I I I 3 2 1 0 I I I I I I OR array 5 4 3 2 1 0 Fixed AND array O O O O O 3 2 1 0 O 0 0 Indicates programmable connection Indicates fixed connection Array-Based Programmable Logic Programmable OR array Fixed OR array Programmable AND array Programmable AND array O O O O O O 3 2 1 3 2 1 PLA PROM PAL

45. 1 X X X 2 1 0 : programmed node NA NA f f 1 0 Programming a PROM

46. More Complex PAL i inputs, j minterms/macrocell, k macrocells From Smith97

47. Configuration A B S F= 0 0 0 0 0 X 1 X 0 Y 1 Y 0 Y X XY X 0 Y XY Y 0 X XY Y 1 X X Y 1 1 0 X X 1 0 Y Y 1 1 1 1 2-input mux as programmable logic block A 0 F B 1 S

48. Logic Cell of Actel Fuse-Based FPGA

49. Look-up Table Based Logic Cell

50. LUT-Based Logic Cell 4 C ....C 1 4 xx xxxx xxxx xxxx Bits D xxxx 4 control Logic xx xx D xx xx function x x 3 xx of xx D 2 xxx D 1 Logic xx xx x function x x of x x xxx F 4 Bits xxxx Logic control xx xx F xx 3 xx function x x xx F of xx 2 xxx F 1 xx xx x xxxxx x H x P Multiplexer Controlled Xilinx 4000 Series by Configuration Program Courtesy Xilinx