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Digital Integrated Circuits - week four -

Digital Integrated Circuits - week four -. Gheorghe M. Ş tefan http://arh.pub.ro/gstefan/ - 2014 -. Tristate buffers. enable = 0, out = hi-z enable = 1, out = in’ Interconnecting two systems : en1=1, en2=0 : System 1 sends, System 2 receives

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Digital Integrated Circuits - week four -

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  1. Digital Integrated Circuits- week four - Gheorghe M. Ştefan http://arh.pub.ro/gstefan/ - 2014 -

  2. Tristate buffers enable = 0, out = hi-z enable = 1, out = in’ Interconnecting two systems: en1=1, en2=0 : System 1 sends, System 2 receives en1=0, en2=1 : System 2 sends, System 1 receives en1=0, en2=0 : System 1 receives, System 2 receives en1=1, en2=1 : forbidden Digital Integrated Circuits - week three

  3. Inverting & non-inverting tristate buffer Digital Integrated Circuits - week three

  4. Transmission gate en = 1 => out = in en = 0 => out = hi-z Main limitation: RON is serially connected to CL Main advantage: no connection to VDD and ground Digital Integrated Circuits - week three

  5. Elementary inverting multiplexor Low power, small area, but low speed Digital Integrated Circuits - week three

  6. Memory circuits Data latches revisited Delay flip-flop (DF-F) Reset-able DF-F Digital Integrated Circuits - week three

  7. Data latches 0 : active level of CK 1 : active level of CK CK = 1 : loop closed CK = 1 : transparent CK = 0 : transparent CK = 0 : loop closed Digital Integrated Circuits - week three

  8. The master-slave structure of DF-F • What is the active edge of clock? • How can the active edge be changed? Digital Integrated Circuits - week three

  9. master-latch is transparent, slave-latch latches • master-latch latches, slave-latch is transparent • the overall structure is anytime non-transparent Digital Integrated Circuits - week three

  10. Reset-able DF-F • The free inverter is substituted by an appropriate gate • Both, master-latch and slave–latch must be “forced” asynchronously Digital Integrated Circuits - week three

  11. Growing – Speeding - Featuring • Size vs. Complexity • Time restrictions in digital systems • Growing the size by composition • Speeding by pipelining • Featuring by closing new loops • The taxonomy of digital systems Digital Integrated Circuits - week four

  12. Size vs. Complexity Size: the dimension of physical resources – Sdigital_system Gate size: the number of CMOS pairs Area size: silicon area Depth: number of logic levels Complexity (algorithmic complexity): ~ the dimension of the shortest description Cdigital_system Simple circuit: Csimple_system <<Ssimple_system Complex circuit: Ccomplex_system ~Scomplex_system Digital Integrated Circuits - week four

  13. Size vs. Complexity (examples) Complex circuit: Simple circuit: Digital Integrated Circuits - week four

  14. Time restrictions in digital systems tin_reg: minimum input arrival time before clock treg_reg : minimum period of clock = Tclock_min = 1/fclock_max tin_out : maximum combinational delay path treg_out : maximum required time after clock Digital Integrated Circuits - week four

  15. Example tin_reg= tp(adder) + tp (selector) + tsu(register) = (550+85+35)ps treg_reg = Tclock_min = 1/fmax= tp(register) + tp(adder) + tp(selector) + tsu(register) = (150+550+85+35)ps fmax= 1.21 GHz tin_out = tp(comparator) = 300ps treg_out = tp(register) + tp(comparator) = (150+300)ps Digital Integrated Circuits - week four

  16. Pipelined connections Digital Integrated Circuits - week four

  17. Blocking – Non-Blocking assignment Blocking assignment: “=“for combinational circuits Non-blocking assignment: “<=“ for edge triggered transitions Digital Integrated Circuits - week four

  18. Fully buffered connection tin_reg=tsu(regsiter) treg_reg = tp(regsiter) + tp(comb) + tsu(regsiter)= 1/fclock_max tin_out : not defined treg_out =tp(regsiter) Digital Integrated Circuits - week four

  19. Growing by composing f(x) = g(h1(x), h2(x), … hm(x) ) Digital Integrated Circuits - week four

  20. Serial & Parallel Composition Digital Integrated Circuits - week four

  21. Example: inner product Digital Integrated Circuits - week four

  22. Example: inner product (cont.) Digital Integrated Circuits - week four

  23. Speeding by pipelining With no pipeline: fclock = 1/(treg+tf+tsu) = 1/(treg+th_1+tg+tsu) Latency: λ = 2 With pipeline: fclock = 1/(treg+ max(th_1+tg)+tsu) Latency: λ = 3 Digital Integrated Circuits - week four

  24. Example: pipelined inner product tp(mult) = 2 ns tp(add) = 1ns tsu(reg) = 20ps tp(reg) = 50ps No pipeline: fck = 0.325 GHz With pipeline: fck = 0.483 GHz Digital Integrated Circuits - week four

  25. Home work 3 Problem 1: design at the gate level an asynchronously reset-able (RST) and preset-able (SET) DF-F. Problem 2: design a synchronously reset-able DF-F. Problem 3: design the test module for the pipelined version of the inner product circuit represented in Figure 3.6 and described in Example 3.7. Use it to simulate the inner product circuit. Digital Integrated Circuits - week three

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