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FSBB 0 Sensor - Tests preparation Main characteristics - Readout – Test systems - HW Gilles CLAUS (on behalf of PICSEL and ALICE teams of IPHC-Strasbourg). Outline. FSBB 0 (Full Scale Building Bloc) Main characteristics Readout FSBB Characterization & HW Interface

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Outline

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  1. FSBB 0 Sensor - Tests preparationMain characteristics - Readout – Test systems - HW Gilles CLAUS (on behalf of PICSEL and ALICE teams of IPHC-Strasbourg)

  2. Outline • FSBB 0 (Full Scale Building Bloc) • Main characteristics • Readout • FSBB Characterization & HW Interface • For FSBB characterisation by IPHC team • For FSBB characterization by ALICE collaborators EUDET Beam Telescope IPHC gilles.claus@iphc.cnrs.fr

  3. 9,2 mm 13,7 mm 16,9 mm Mistral B Mistral A Astral 27,6 mm FSBB 0 : MISTRAL & ASTRAL • Two versions : MISTRAL & ASTRAL • Three FSBB 0 submitted in One single chip • Chip ~ Equivalent size as FSP (Full Scale Prototype) • Two MISTRAL (M0a, M0b) • One ASTRAL (A0) • MISTRAL T r.o 41,6 µs - ASTRAL T r.o 20,8 µs • Chip organisation  3 Sensors in one chip • Each sensor has its own steering & readout – Common power bus • 3 Matrix 9,2 x 13,7 mm² - 416 x 416 pixels – Pixels 22 x 33 µm² • Steering: • Reset + FSBB Configuration (operating mode, bias, … ) by JTAG slow control • Input clock @ 160 MHz • Start signal (to synchronize the readout of multiple FSBB) • Readout: • Normal operation mode (After zero suppression)  4 Wires link @ DDR 640 Mb/s • Test modes (Analogue & Digital) to characterize pixels, discriminators • Digital : 4 Wires protocol • Analogue : 16 Analogue outputs IPHC gilles.claus@iphc.cnrs.fr

  4. 9,2 mm Pixel Array 13,7 mm SUZE Test PADS Serial Output Readout Control JTAG TMS TDO TCK RST TDI CLK_D MK_D Start D0 D1 CK (160 MHz) JTAG (CMOS) Data out (LVDS) (LVDS) FSBB 0 : MISTRAL & ASTRAL • Steering & readout signals • Steering 5 CMOS + 2 LVDS • JTAG  5 CMOS lines • RST, TMS, TCK : Common all sensors • TDI, TDO : Daisy chained • Clock in (160 MHz)  1 LVDS • Start in  1 LVDS • Readout (640 Mb/s)  4 LVDS • MK_D (Synchro)  1 LVDS • CLK_D (160 MHz)  1 LVDS • Data D0, D1 DDR 320 Mb/s  2 LVDS • Testability  Test points : 11 Analogues + 2 Digital CMOS • MISTRAL • 4 VRef discri + 3 VTests discri • 4 bias • 2 digital (CMOS)  Spy internal signals • ASTRAL • 3 VRef discri • 2 Bias • 2 digital (CMOS)  Spy internal signals IPHC gilles.claus@iphc.cnrs.fr

  5. Full Scale Building Block (FSBB 0): MISTRAL & ASTRAL • Testabilityimplemented on FSBB : • Sensors configuration and status JTAG slow control (5 wires link) • Digital pads interconnection testing  JTAG boundary scan • Pixel characterization at analogue level  Analogue outputs of 8 columns  Fe55, Calibration peak, CCE, Noise • All discriminators characterization  Discri input = On-chip analogue signal  Scurve : Noise, Pedestal • All Pixel + discriminators characterization  Scurve : Noise, Pedestal + Fake hits rate • Data transmission & SUZE02 logic test  Pixels patterns emulation by JTAG • Sensor temperature  Read as analogue (2 pads) • Spy internal digital & analogue signals  2 LVDS test pads + n Analogues test pads EUDET Beam Telescope IPHC gilles.claus@iphc.cnrs.fr

  6. Running FSBB 0 • Power on • Apply power supply (Single 5V : On board 1,8 V regulator) • Provide a 160 MHz clock • Generate a reset (No power on reset) • Configuration • Initialize all JTAG registers to select the operating mode • We can provide JTAG configuration SW + Ready to use configuration files • Start FSBB • Send a JTAG “start command”  To run one single FSBB • Activate the HW “Start signal”  To run multiple FSBB synchronized • Readout • Synchronize DAQ on FSBB clock out (CLK_D 160 MHz) • Detect beginning of frame by either • MK_D signal • Header on D0, D1 • Deserialize (DDR) the data stream provided by D00, D01 IPHC gilles.claus@iphc.cnrs.fr

  7. FSBB 0 Normal Readout & Data stream • Readout configuration: • Double Data Rate (DDR) @ 160 MHz  320 Mbit/s • Two options • Full memory : Two data link DDR @ 160 MHz  640 Mbit/s • Half memory : One data link DDR @ 160 MHz  320 Mbit/s • Data stream organization • Data generated on both edges (DDR) of FSBB output clock • Synchronization signal MKD • Data LSB first • Data stream is organized in 30 bits words multiplexed over the two links • First bit of frame = LSB of Header (30 bits) Two links @ 320 Mbit/s One link @ 320 Mbit/s IPHC gilles.claus@iphc.cnrs.fr

  8. FSBB 0 Data stream : Service & Data fields • Data words: 30 bits  W30 (30 bits words) • Mono output: • Dual output: • Data generated on both edges (DDR) of FSBB output clock @ 160 MHz (Bit time slot = 3,125 ns) • Service fields  Total 4 W30 / output • Header  1 W30 / output (Header 0 + Header 1) • Trigger  1 W30 / output • Frame counter, data length  1 W30 / output • Trailer  1 W30 / output (Trailer 0 + Trailer 1) • Data fields ( format on next slide ) • MISTRAL  Maximum = 416 x W30 / output • ASTRAL  Maximum = 208 x W30 / output • Total data stream size per output • MISTRAL  Max 13 312 bits / Output / 41,6 µs  Total (2 outputs) 76 MB/s • ASTRAL  Max 6 656 bits / Output / 20,8 µs  Total (2 outputs) 76 MB/s IPHC gilles.claus@iphc.cnrs.fr

  9. The useful data is the daisy chain of "status" and "hit-windows" Status:  "FSBB user manual" for details One status field per super line Indicates row address + the number of Hit-Windows Hit-windows:  "FSBB user manual" for details Up to 9 hit-windows / ½ line Indicates : column address + Hit map + Window offset in super Line G1 G0 416 224 223 0 … … Delta (2bits) 3 State 0 Super Line X 2 State 0 1 State 1 0 State 1 3 Super Line X-1 2 1 0 FSBB 0 Data stream : Data fields format IPHC gilles.claus@iphc.cnrs.fr

  10. FSBB 0 Test Readout & Data stream • Specific protocols for test mode readout • Bias - DAC characterization • Analogues test pads to measure DAC outputs • DAC configuration by JTAG • Analogue test mode for pixels characterisation • 8 Analogue columns • 16 Analogues outputs (2 rows read at the same time) • Synchonization via CLK_A and MK_A (same pads as CLK_D, MK_D) • Digital test mode for Discriminators & (Pixels + Discriminators) characterization • Uses the the “4 wires link” • The FSBB 0 operation mode selection (Normal / Test) is done by JTAG • Protocols explanation • Uses normal readout pads + 16 Analogue outputs (@ 10 MHz - MISTRAL / 20 MHz ASTRAL) • Explanation requires one more talk of ~ 15 minutes  On one of WP5 April session • FSBB 0 User manual IPHC gilles.claus@iphc.cnrs.fr

  11. FSBB 0 Characterization @ IPHC : At laboratory • Characterization protocol at laboratory • Using FSBB 0 “Test modes” • Analogue pixels (8 columns)  Noise, Fe55 Calibration peak, CCE • Discriminators & Pixels + Discriminators  S curves (Noise, Pedestal distribution) + Fake hits rate + Reaction to Fe55 • Normal readout • Test data transmission (Service fields + Data fields) – Check SUZE02 logic (Emulated pattern) • Should start on beginning of June 2014 • Test bench requirements Analogue test bench FSBBProximity board Slow Control ( JTAG )FSBB configuration 2 x IPHC USB ADC8 Inputs – 12 bits – 50 MHz Noise, Calibration peack, CCE Digital test bench JTAG via PC // Port • S Curves • Normal readout NI PXI 65628 Inputs DDR up to 400 Mb/s IPHC gilles.claus@iphc.cnrs.fr

  12. FSBB 0 Characterization @ IPHC : Beam Test • Beam Test • FSBB running in Normal readout mode only • Beam Telescope  Detection efficiency, Spatial resolution (No test of analogue part) • Four reference planes  FSBB • Two DUT planes  FSBB • Should be ready for October 2014 • Test bench requirements DAQ SystemTwo options NI PXIe Flex RIO • NI Flex RIO 7962R board • New NI 6587 DDR front-end • FW upgrade • SW upgrade • Low / No dead time • Manpower Beam Telescope Profile view Beam Telescope Front view NI PXI 6562 • NI PXI 6562 board • SW upgrade • High / Medium dead time • Manpower DUT Référence planes IPHC gilles.claus@iphc.cnrs.fr

  13. FSBB 0 Characterization @ ALICE : HW & SW • Two proximity PCB will be developed @ IPHC • PCB No 1 for MISTRAL M0a or ASTRAL A0 • PCB No 2 for MISTRAL M0b • Schematics & components list for ~ 15 April 2014 • PCB available for ~ 1 June 2014 • How many PCB ? • JTAG SW • Windows GUI • Uses PC // port or any PIO via user DLL • Configurations saved from GUI in text files • Interface to DAQ via COM (Component Object Model) • Should be ready for ~ 1 June 2014 • Test modes protocol • Analogue pixel readout (8 columns) • Discriminators – Pixels + discriminators « S » curves • FSBB User manual should be ready for ~ 1 April PCB No1 – MISTRAL M0a (M0b power + jtag) PCB No1 – ASTRAL A0 PCB No2 – MISTRAL M0b (M0a power + jtag) IPHC gilles.claus@iphc.cnrs.fr

  14. FSBB 0 Characterization @ ALICE : Proximity PCB Mimosa 28 PCB • Power supply “Alim” • Single + 5V <= 500 mA • Shunts to measure IVdda, IVddd • Analogue outputs • ERNI 50 Pins connector • Same mapping as Mi26-Mi28 • JTAG – RJ45 - LVDS • 8 - TDO* • 7 - TDO • 6 - TMS* • 5 - TMS • 4 - TDI* • 3 - TDI • 2 - TCK* • 1 - TCK • CTRL – RJ45 – LVDS • 8 - SPEAK*  Start analogue test mode • 7 - SPEAK • 6 - RST*  FSBB reset • 5 - RST • 4 - START*  Start normal readout mode • 3 - START • 2 - CLK*  External clock if required • 1 - CLK There is on board 160 MHz oscillator • DATA – RJ45 - LVDS • 8 - D1*  Data line D1 • 7 - D1 • 6 - D0*  Data line D0 • 5 - D0 • 4 - MK  Frame synchronization signal • 3 - MK* • 2 - CK*  Output clock (160 MHz) • 1 - CK Same connectors as Mimosa 26/28 PCB Mimosa 28 PCB documentation – M.Goffe IPHC IPHC gilles.claus@iphc.cnrs.fr

  15. Summary • FSBB 0 documentation • This talk contains general informations about normal readout & PCB interface • Detailed documentation for ~ 1 April 2014  FSBB User manual • Proximity board for ALICE collaborators • Schematics & Components list available for ~ 15 April 2014 • PCB(Component assembly + FSBB bonding done by collaborators) available for ~ 1 June 2014 • Operational (characterized ?) FSBB mounted on PCB available for ~ 1 July 2014 ? • JTAG SW to configure FSBB • Available for ~ 1 June 2014 • FSBB characterization should start on June 2014 @ IPHC • 9 June 2014 Integration & “Smoke test” • 16 June 2014 start characterization EUDET Beam Telescope IPHC gilles.claus@iphc.cnrs.fr

  16. Backup IPHC gilles.claus@iphc.cnrs.fr

  17. Full Scale Sensors (FSS): MISTRAL & ASTRAL • Sensor organisation: • Composed of 3 x FSBB (Full Scale Building Block) • Matrix 1 cm x 1,3 cm - 416 x 416 pixels – Pixels pitch 24 µm x 33 µm • ASTRAL (in-pixel discriminator) T r.o ~ 20 µs or MISTAL (column discriminator) T r.o ~ 35 µs • One serial output ~ 1 Gb/s 8B/10B protocol  Will use the INFN design • Main clock 160 MHz or 40 MHz if on-chip PLL implemented • Steering: • FSS Configuration (operating mode, bias, … ) by JTAG slow control • FSS Start command: • By external HW signal (Telescope or ladder setup) • By JTAG slow control (single MISTRAL or ASTRAL setup) • Readout: • Normal zero suppression output • Analogue test mode to characterize pixels (8 columns) • Digital test mode to characterize Discriminators & Pixels + Discriminators IPHC gilles.claus@iphc.cnrs.fr

  18. 3 cm Pixel Array Pixel Array Pixel Array SUZE SUZE SUZE JTAG Test PADS Serial Output Readout Controller PLL TDO TMS TCK RST TDI Data out (LVDS) Start CK (40 MHz) CK (160 MHz) Only one output 8B/10B protocol@ ~ 1 Gb/s JTAG (CMOS) (LVDS) (LVDS) Input clock 40 MHz Via on-chip PLL Full Scale Sensors (FSS): MISTRAL & ASTRAL • Steering & readout signals • Steering  4-5 CMOS + 2 LVDS / Ladder • JTAG  4 (5) CMOS lines / ladder • RST, TMS, TCK : Common all sensors • TDI, TDO : Daisy chained • Clock in  1 LVDS / ladder • Start in  1 LVDS / ladder (Optional ? ) • Readout  1 LVDS / Sensor • Data out 8B/10B  1 LVDS / sensor • Testability  0 Pads / Ladder • No pads required on the ladder • Pads required for probe testing  Nb ? • 2 LVDS outputs  4 pads • 8 Analogue outputs  8 pads • 1 Input to characterization ADC  1 pad • N Analogue internal references  N IPHC gilles.claus@iphc.cnrs.fr

  19. Full Scale Sensors (FSS): JTAG Slow control Slow Control ( JTAG ) – Mimosa 26 configuration • TCK frequency • Using PC // port  Few 100 Khz • Mimosa / FSBB limits  10 – 20 MHz • Run on STAR Experiment @ 1,5 MHz JTAG via PC // Port IPHC gilles.claus@iphc.cnrs.fr

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