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An Introduction to Verilog-A: Transitioning from Verilog

An Introduction to Verilog-A: Transitioning from Verilog. Tutorial 1. Lesson Plan (Tentative). Week 1: Transitioning from VHDL to Verilog, Introduction to Cryptography Week 2: A5 Cipher Implementaion, Transitioning from Verilog to Verilog-A Week 3: Verilog-A Mixer Analysis.

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An Introduction to Verilog-A: Transitioning from Verilog

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  1. An Introduction to Verilog-A: Transitioning from Verilog Tutorial 1

  2. Lesson Plan (Tentative) • Week 1: Transitioning from VHDL to Verilog, Introduction to Cryptography • Week 2: A5 Cipher Implementaion, Transitioning from Verilog to Verilog-A • Week 3: Verilog-A Mixer Analysis

  3. Analog Verilog (Verilog-AMS) • Verilog introduced as IEEE Standard 1364 • Dire need for analog circuits to be modelled as a language • VHDL and Verilog come up with analog equivalents: AHDL and Verilog-AMS (Analog and Mixed Signal)

  4. New Types in Verilog-A • Integer/Real (same as Verilog) • Electrical (electrical wire) • Parameter (parameter constants) • Genvar (local variables eg for loops and such)

  5. Parameters • Example: Parameter real gain = 1 from [1:1000]; • Second keyword real specifies optional type (real or integer) • From is used to specifies optional range of the parameter. [] is used to indicate that the end values are allowable while () means end values are not.

  6. Parameters • Parameters cannot be changed at run time, but can be changed at compile time using defparam • Example: module annotate; defparam tgate.m1.gate_width = 5e-6, tgate.m2.gate_width = 10e-6; endmodule

  7. Parameters • Can also exclude ranges, eg Parameter real res = 1.0 from [0:inf) exclude (10:20) exclude 100; • Can be arrayed, eg Parameter real poles[0:3] = {1.0, 2.0, 3.83, 4.0}; • Can be strings, eg Parameter string type = “NPN” from { “NPN”, “PNP” };

  8. Operators • Mostly same as Verilog, but has extra functions for analog design • Built-in mathematical functions: • ln(x), log(x), exp(x), sqrt(x), min(x,y), max(x,y), abs(x), pow(x,y), floor(x), ceil(x) • sin(x), cos(x), tan(x), asin(x), acos(x), atan(x), sinh(x), cosh(x), tanh(x), asinh(x), acosh(x), atanh(x)

  9. Operators (con’t) • Voltage/Current access: • V(b1), V(n1) access the branch voltage and node voltage wrt ground • V(n1,n2) accesses the difference between n1 and n2 • I(b1), I(n1) access the branch current and node current flowing to ground

  10. Operators (con’t) • Voltage/Current access: • I(n1,n2) accesses the current flowing between n1 and n2 • I(<p1>) accesses the current flowing into p1, a port

  11. Analog Operators (Filters) • Cannot be placed in any loop or conditional (for, while, if, case, repeat) because internal state must be maintained • Only in an analog block • Argument list cannot be null

  12. Analog Operators • ddt(x), calculates the time derivative of x • idt(x,opt_ic), calculates the time integral of x (with or without initial condition) • laplace_zp, laplace_zd, laplace_np, laplace_nd (various laplace transforms)

  13. Analog Operators • Analysis types • Analysis() returns true(1) if analysis done is of that type (AC, DC, tran, noise, etc) • Noise models • Can use white_noise, flicker_noise, noise_table

  14. Syntax: analog function real geomcalc; input l, w ; output area, perim ; real l, w, area, perim ; begin area = l * w ; perim = 2 * ( l + w ); end endfunction Called as follows: dummy = geomcalc(l-dl, w-dw, ar, per) ; User-Defined Functions

  15. Signals and Models • Let’s take an example of a resistor (modelled as a voltage-controlled current source) module my_resistor(p,n); parameter real R=1; electrical p,n; branch (p,n) res; analog begin V(res) <+ R * I(res); end endmodule

  16. Signals and Models (con’t) • Other current/voltage sources: • V(out) <+ A * V(in); //VCVS • I(out) <+ A * V(in); //VCCS • V(out) <+ A * I(in); //CCVS • I(out) <+ A * I(in); //CCCS

  17. Signals and Models • RLC Circuit model • Series: V(p, n) <+ R*I(p, n) + L*ddt(I(p, n)) + idt(I(p, n))/C; • Parallel: I(p, n) <+ V(p, n)/R + C*ddt(V(p, n)) + idt(V(p, n))/L;

  18. Simple Amplifier • Example: module amp(out, in); input in; output out; electrical out, in; parameter real Gain = 1; analog V(out) <+ Gain*V(in); endmodule

  19. Example: one-bit DAC module onebit_dac (in, out); input in; inout out; wire in; electrical out; real x; analog begin if (in == 0) x = 0.0; else x = 3.0; V(out) <+ x; end endmodule Note that wires are used with electricals. The digital signals in this context are represented as bits Mixed Signal Models

  20. Conclusions • Verilog is so useful that it has been redesigned for analog/mixed signal applications • Designer Guide (surprisingly easy to read) http://www.designers-guide.org/VerilogAMS/VlogAMS-2.1-pub.pdf

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