1 / 34

Modern GPU Architectures

Modern GPU Architectures. Varun Sampath University of Pennsylvania CIS 565 - Spring 2012. Agenda/GPU Decoder Ring. Fermi / GF100 / GeForce GTX 480 “Fermi Refined” / GF110 / GeForce GTX 580 “Little Fermi” / GF104 / GeForce GTX 460 Cypress / Evergreen / RV870 / Radeon HD 5870

lyle
Télécharger la présentation

Modern GPU Architectures

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Modern GPU Architectures Varun Sampath University of Pennsylvania CIS 565 - Spring 2012

  2. Agenda/GPU Decoder Ring • Fermi / GF100 / GeForce GTX 480 • “Fermi Refined” / GF110 / GeForce GTX 580 • “Little Fermi” / GF104 / GeForce GTX 460 • Cypress / Evergreen / RV870 / Radeon HD 5870 • Cayman / Northern Islands / Radeon HD 6970 • Tahiti / Southern Islands / GCN / Radeon HD 7970 • Kepler / GK104 / GeForce GTX 680 • Future • Project Denver • Heterogeneous System Architecture

  3. From G80/GT200 to Fermi • GPU Compute becomes a driver for innovation • Unified address space • Control flow advancements • Arithmetic performance • Atomics performance • Caching • ECC (is this seriously a graphics card?) • Concurrent kernel execution & fast context switching

  4. Unified Address Space • PTX 2.0 ISA supports 64-bit virtual addressing (40-bit in Fermi) • CUDA 4.0+: Address space shared with CPU • Advantages? Image from NVIDIA

  5. Unified Address Space cudaMemcpy(d_buf, h_buf, sizeof(h_buf), cudaMemcpyDefault) • Runtime manages where buffers live • Enables copies between different devices (not only GPUs) via DMA • Called GPUDirect • Useful for HPC clusters • Pointers for global and shared memory are equivalent

  6. Control Flow Advancements • Predicated instructions • avoid branching stalls (no branch predictor) • Indirect function calls:call{.uni}fptr, flist; • What does this enable support for?

  7. Control Flow Advancements • Predicated instructions • avoid branching stalls (no branch predictor) • Indirect function calls:call{.uni}fptr, flist; • What does this enable support for? • Function pointers • Virtual functions • Exception handling • Fermi gains support for recursion

  8. Arithmetic • Improved support for IEEE 754-2008 floating point standards • Double precision performance at half-speed • Native 32-bit integer arithmetic • Does any of this help for graphics code?

  9. Cache Hierarchy • 64KB L1 cache per SM • Split into 16KB and 48KB pieces • Developer chooses whether shared memory or cache gets larger space • 768KB L2 cache per GPU • Makes atomics really fast. Why? • 128B cache line • Loosens memory coalescing constraints

  10. The Fermi SM • Dual warp schedulers – why? • Two banks of 16 CUDA cores, 16 LD/ST units, 4 SFU units • A warp can now complete as quickly as 2 cycles Image from NVIDIA

  11. The Stats Image from Stanford CS193g

  12. The Review in March 2010 • Compute performance unbelievable, gaming performance on the other hand… • “The GTX 480… it’s hotter, it’s noisier, and it’s more power hungry, all for 10-15% more performance.” – AnandTech (article titled “6 months late, was it worth the wait?”) • Massive 550mm2 die • Only 14/16 SMs could be enabled (480/512 cores)

  13. “Fermi Refined” – GTX 580 • All 32-core SMs enabled • Clocks ~10% higher • Transistor mix enables lower power consumption

  14. “Little Fermi” – GTX 460 • Smaller memory bus (256-bit vs 384-bit) • Much lower transistor count (1.95B) • Superscalar execution: one scheduler dual-issues • Reduce overhead per core? Image from AnandTech

  15. A 2010 Comparison NVIDIA GeForce GTX 480 ATI Radeon HD 5870 1600 cores 153.6 GB/s memory bandwidth 2.72 TFLOPS single precision 2.15 billion transistors • 480 cores • 177.4 GB/s memory bandwidth • 1.34 TFLOPS single precision • 3 billion transistors Over double the FLOPS for less transistors! What is going on here?

  16. VLIW Architecture • Very-Long-Instruction-Word • Each instruction clause contains up to 5 instructions for the ALUs to execute in parallel + Save on scheduling and interconnect (clause “packing” done by compiler) - Utilization Image from AnandTech

  17. Execution Comparison Image from AnandTech

  18. Assembly Example AMD VLIW IL NVIDIA PTX

  19. The Rest of Cypress • 16 Streaming Processors packed into SIMD Core/compute unit (CU) • Execute a “wavefront” (a 64-thread warp) over 4 cycles • 20 CUs * 16 SPs * 5 ALUs = 1600 ALUs Image from AnandTech

  20. Performance Notes • VLIW architecture relies on instruction-level parallelism • Excels at heavy floating-point workloads with low register dependencies • Shaders? • Memory hierarchy not as aggressive as Fermi • Read-only texture caches • Can’t feed all of the ALUs in an SP in parallel • Fewer registers per ALU • Lower LDS capacity and bandwidth per ALU

  21. Optimizing for AMD Architectures • Many of the ideas are the same – the constants & names just change • Staggered Offsets (Partition camping) • Local Data Share (shared memory) bank conflicts • Memory coalescing • Mapped and pinned memory • NDRange (grid) and work-group (block)sizing • Loop Unrolling • Big change: be aware of VLIW utilization • Consult the OpenCL Programming Guide

  22. AMD’s Cayman Architecture – A Shift • AMD found average VLIW utilization in games was 3.4/5 • Shift to VLIW4 architecture • Increased SIMD core count at expense of VLIW width • Found in Radeon HD 6970 and 6950

  23. Paradigm Shift – Graphics Core Next • Switch to SIMD-based instruction set architecture (no VLIW) • 16-wide SIMD units executing a wavefront • 4 SIMD units + 1 scalar unit per compute unit • Hardware scheduling • Memory hierarchy improvements • Read/write L1 & L2 caches, larger LDS • Programming goodies • Unified address space, exceptions, functions, recursion, fast context switching • Sound Familiar?

  24. Radeon HD 7970: 32 CUs * 4 SIMDs/CU * 16 ALUs/SIMD = 2048 ALUs Image from AMD

  25. Image from AMD

  26. NVIDIA’s Kepler NVIDIA GeForce GTX 680 NVIDIA GeForce GTX 580 512 SPs 40nm process 192.4 GB/s memory bandwidth 244W TDP 1/8 double performance 3 billion transistors • 1536 SPs • 28nm process • 192.2 GB/s memory bandwidth • 195W TDP • 1/24 double performance • 3.5 billion transistors • A focus on efficiency • Transistor scaling not enough to account for massive core count increase or power consumption • Kepler die size 56% of GF110’s

  27. Kepler’s SMX • Removal of shader clock means warp executes in 1 GPU clock cycle • Need 32 SPs per clock • Ideally 8 instructions issued every cycle (2 for each of 4 warps) • Kepler SMX has 6x SP count • 192 SPs, 32 LD/ST, 32 SFUs • New FP64 block • Memory (compared to Fermi) • register file size has only doubled • shared memory/L1 size is the same • L2 decreases Image from NVIDIA

  28. Performance • GTX 680 may be compute regression but gaming leap • “Big Kepler” expected to remedy gap • Double performance necessary Images from AnandTech

  29. Future: Integration • Hardware benefits from merging CPU & GPU • Mobile (smartphone / laptop): lower energy consumption, area consumption • Desktop / HPC: higher density, interconnect bandwidth • Software benefits • Mapped pointers, unified addressing, consistency rules, programming languages point toward GPU as vector co-processor

  30. The Contenders • AMD – Heterogeneous System Architecture • Virtual ISA, make use of CPU or GPU transparent • Enabled by Fusion APUs, blending x86 and AMD GPUs • NVIDIA – Project Denver • Desktop-class ARM processor effort • Target server/HPC market? • Intel • Larrabee Intel MIC

  31. References • NVIDIA Fermi Compute Architecture Whitepaper. Link • NVIDIA GeForce GTX 680 Whitepaper. Link • Schroeder, Tim C. “Peer-to-Peer & Unified Virtual Addressing” CUDA Webinar. Slides • AnandTech Review of the GTX 460. Link • AnandTech Review of the Radeon HD 5870. Link • AnandTech Review of the GTX 680. Link • AMD OpenCL Programming Guide (v 1.3f). Link • NVIDIA CUDA Programming Guide (v 4.2). Link

  32. Bibliography • Beyond3D’s Fermi GPU and Architecture Analysis. Link • RWT’s article on Fermi. Link • AMD Financial Analyst Day Presentations. Link

More Related