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Digital Logic Circuits

CHAPTER 13. Digital Logic Circuits. Figure 13.1. Voltage analog of internal combustion engine in-cylinder pressure. Figure 13.1. 13-1. Digital representation of an analog signal. Figure 13.2. Figure 13.2. 13-2. A binary signal. Figure 13.3. Figure 13.3. 13-3. Table 13.1.

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Digital Logic Circuits

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  1. CHAPTER13 Digital Logic Circuits

  2. Figure 13.1 Voltage analog of internal combustion engine in-cylinder pressure Figure 13.1 13-1

  3. Digital representation of an analog signal Figure 13.2 Figure 13.2 13-2

  4. A binary signal Figure 13.3 Figure 13.3 13-3

  5. Table13.1

  6. Complements and Negative Numbers Sign-magnitude convention Example of Twos Complement Operation ( cf : 92 – 114 = - 22)

  7. Digital Code Systems BCD code Hexadecimal code Three-bit Gray code

  8. Figure 13.11, Table 13.9 Logical addition and the OR gate Rules for logical addition (OR) Figure 13.11 Table 13.9 13-4

  9. Figure 13.12, Table 13.10 Logical multiplication and the AND gate Rules for logical multiplication (AND) Figure 13.12 Table 13.10 13-5

  10. Figure 13.13 Example of logic function implementation with logic gates Figure 13.13 13-6

  11. Table 13.11

  12. Figure 13.17 De Morgan’s laws Figure 13.17 13-7

  13. Figure 13.18 Sum-of-products and product-of-sums logic functions Figure 13.18 13-8

  14. Figure 13.21 Equivalence of NAND and NOR gates with AND and OR gates Figure 13.21 13-9

  15. Figure 13.23 Figure 13.23 13-10

  16. Figure 13.24 NOR gate as an inverter Figure 13.24 13-11

  17. Figure 13.27, 13.28 XOR gate Realization of an XOR gate Figure 13.27 Figure 13.28 13-12

  18. Figure 13.29

  19. Figure 13.30 Truth table and Karnaugh map representations of a logic function Figure 13.30 13-13

  20. Figure 13.31 Karnaugh map for a four-variable expression Figure 13.31 13-14

  21. One- and two-cell subcubes for the Karnaugh map of Figure 13.31 Figure 13.32 Figure 13.32 13-15

  22. Figure 13.34 Karnaugh map for the function W ·X· Y · Z + W · X · Y · Z + W · X · Y · Z + W · X · Y · Z Figure 13.34 13-16

  23. Figure 13.46, 13.47

  24. Figure 13.55 4-to-1 MUX Figure 13.55 13-17

  25. Figure 13.56 Internal structure of the 4-to-1 MUX Figure 13.56 13-18

  26. Figure 13.57, Table 13.13 Functional diagram of four-input MUX Table 13.13 Figure 13.57 13-19

  27. Figure 13.58 Read-only memory Figure 13.58 13-20

  28. Figure 13.59

  29. A 2-to-4 decoder Internal organization of SRAM

  30. An example of PLD (Programmable Logic Device; GAL16V8) Simple Mode Logic Diagram OLMC (Output Logic Macrocell):Register Mode

  31. Figure 13.65 Programming Example by using a HDL (Hardware description language)

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