Creation of SiGe Radhard Library AMICSA 2006

1. Creation of SiGe Radhard LibraryAMICSA 2006 H.-V. Heyer1, U. Jagdhold2 Kayser-Threde GmbH1 Wolfratshauser Str. 48 81379 München Germany

2. Outline • Introduction • Goal • Characterization of the Existing Technology • New Layout Rules at Transistor Level • New Design Rules at Design Level • Outlook • Example Local Oscillator (The SiMs and 30/20 Projects) • Conclusion

3. Introduction I • “High Frequency SiGe MMICs for Converter and Local Oscillators” (SiMs) survey demonstrates that the best candidate for optimal integration of microwave elements with high performance is the SiGe Technology (ESA TRP study) • Microwave components (especially the Local Oscillator) for functional elements of communication equipments in space fit well with the performance to be achieved • SiMs Study has identified IHP as best foundry for the SiGe components in up and down converters in space • SiGe BiCMOS Technology is already a Radiation hard Technology according to Cressler ( Silicon-Germanium Heterojunction Bipolar Transistors, chapter 3 “SiGe HBT BiCMOS Technology”) • Basic tests of the SGB25VD Technology shall demonstrate the Cressler statement (ESA ARTES 5 Programme)

4. Introduction II • IHP is interested in the dedicated market for space and nuclear components market • The RF experience needed is already existing from a lot of research projects • Missing is radiation experience for IHP technology • IHP has started a Radiation hardened Library Project to overcome this lack of experience • This presentation will demonstrate the current und future activities of this project at IHP

5. Goal • Radiation hardened components for the use in space projects as products in Multi-project-wavers MPW • Radiation hardened components for the nuclear industry & research • Radiation hardened library for SGB25VD Technology • Radiation Hardness in the Level of 200 krad total dose • Radiation Hardness by Design of the Transistors Layouts • Radiation Hardness by Design Methods (e. g. Voter) • No change in the existing Technology SGB25VD

6. Characterization of the Existing Technology I • Characterization of the existing Technology is done in the following steps Characterization for very high dose rates and high dose levels (Mrad/s and 100Mrad total dose) Customers are the nuclear research facilities and their industries Test of basic structures, facility is CNM in Spain (Barcelona) Technology is already under tests Characterization for medium and low dose rates ( 2rad/s and 002rad/s up to 200Krad total dose) Customer isthe space industry Test of basic structures within the 30/20 project (TID,SEE,NIEL tests), facility GfS Munich Germany, and RADEF Jyväskylä Finland

7. Characterization of the Existing Technology II Fig.1: Current Gain Degradation of Bipolar Transistors Radiation and Measurement done at CNM Barcelona

8. Characterization of the Existing Technology III Radiation test of the 30/20 Project Fig.2: Radiation Test Circuit Circuit Contains: Bipolar Transistors N-Mos Transistors P-Mos Transistors Bipolar Oscillator MOS Oscillator MOS Shiftregister Following Tests will be performed: Total Dose Test using Co60 up to 200krad Displacement Damage Test using proton beam up to 1012 protons/cm2 Single Event Upset and Latchup Test using heavy ion beam 1011 ions/cm2

9. Characterization of the Existing Technology IV Fig.3: Test Board with Bonded Chips and Wiring Fig.4: Test Equipment with Wiring

10. Characterization of the Existing Technology V Fig. 5: Schematic of the Local Oscillator Project 30/20, Radiation Hardness will be tested

11. Characterization of the Existing Technology VI • New Test Chip will be made to characterize MIM`s , Interconnection, Resistors, and Diodes

12. New Layout Rules at Transistor Level I • New DRC Rules on Transistor Level Disabling of Latchup Rules is Forbidden Gate Poly extension of MOS gate is limited to max. 1.41 microns PWell and Nwell contact rings must have dimensions less than 12 microns All Devices must be located within contacted NWell/PWell Ring Gate Poly have not to cross any well border Gate Poly must be within NWell or Pwell Active Shapes on different nets must be shielded with well contact

13. New Layout Rules at Transistor Level II Fig. 6: Radiation Hard Design Rule incorporation to DFII from Cadence

14. New Layout Rules at Transistor Level III Fig.7: Inverter Design after new Radiation Hardness Rules after G. Anelli, Ref.[1] No Poly extensions over wells Pwell + Contacts

15. New Layout Rules at Transistor Level IV Base Emitter Collector Fig. 8: Bipolar Transistor with PWell Ring and Contact Pwell Ring with Ground Contact

16. D Q > voter Input Output D Q > CLK D Q > New Design Rules at Design Level I • Cell Level: New Voter Cell • Solution for Latch-up and Single Event Upset • Drawback: Additional Area Fig. 9: Voter Cell for Triple Module Redundancy after S. Habinc, Ref.[3]

17. FT memory (cache) exception (cache miss) parity generation parity check memory controller New Design Rules at Design Level II • System Level: Cache memory with parity protection Fig. 10: Cache with parity, Ref. [3] Solution for Latch-up, Single Event Upset Drawback: Additional Hardware

18. New Design Rules at Design Level III • Cell Level: IO corner cell with Latch-up detection • System Level: Power down Latch_up detection Fig. 11: Latch up detector Solution for Latch-up Drawback: New Start of the Chip

19. Outlook I • Example Local Oscillator (The SiMs and 30/20 Projects) • Basic Structure radiation test schedule of 30/20

20. Outlook II • Local Oscillator radiation test schedule of 30/20

21. Outlook III • Start of New Project Radiation Hardness March 2006 • Development of additional Test structures Oct. 2006 • Creation of a new CMOS Rad Hard Library Dec. 2006 • Design of a Rad Hard Test Device, e.g. Leon3ft Jan. 2007 • Preparation of the Test Device April 2007 • Radiation Tests of the Test Device (in Cooperation)

22. Conclusion • By using our inhouse BiCMOS Technology, it should be possible by applying new Design Rules and new Libraries to make circuits resistant against any kind of Radiation. • Short Term: early access to Rad Hard Silicon • Long Term: enclose a new market segment for IHP

23. Literature • References • [1] Giovanni Anelli, “Radiation-hard circuits in deep submicron • CMOS technologies”, CERN, Microelectronics Group, • Switzerland • [2] Ulrich Trunk “Strahlenschäden in Integrierten Schaltungen” ASIC Labor Heidelberg, Physikalisches Institut der • Universität Heidelberg, He Seminar, 2.Juli 2002, • [3] Sandi Habinc, “Functional triple modular redundancy (FTMR) VHDL design methodology for redundancy in combinatorial and • sequential logic” – Design and assessment report, Gaisler • Research, Inc.

24. Physics • Radiation: Leptonen, Bosonen, Baryonen, Mesonen Electrons, X-Ray, • Protons, Neutrons, Alpha Particles, Heavy Ions… • Energy: 10-4 – 106 MeV • Impact on Transistors: CMOS: Leakage of Transistors 1pA->1nA Drain Current change Bipolar: current gain degradation • Impact on Circuitry: IC-Level Leakage, Latch-up, Single Event Upset • Advantages: CMOS: for 0.25 micron Processes Vt-Change no concern Bipolar: has already a guard ring, and there is always a current running through the device, Latch-up no concern

25. Solution = Hardening by Design I • Transistor Level: Guard Rings, Metal connection between Transistors many bulk contacts • Solution for Latch-up, IC-Level Leakage • Drawback: Area will be increased After G. Anelli, Ref.[1] Folie von G. Schoof