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Digital Control of Power “a Different Way of Thinking”

Digital Control of Power “a Different Way of Thinking”. Rob de Nie Digital Control of Power TUE guest lecture 05, OCT, 2010. Outline. 0. 1. 1. 0. 1. 0. 0. 1. Pro’s & Con’s Example Closing the Loop Communication Simulation Prototyping Conclusions.

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Digital Control of Power “a Different Way of Thinking”

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  1. Digital Control of Power“a Different Way of Thinking” Rob de Nie Digital Control of Power TUE guest lecture 05, OCT, 2010

  2. Outline 0 1 1 0 1 0 0 1 Pro’s & Con’s Example Closing the Loop Communication Simulation Prototyping Conclusions Digital Control of Power / Innovation-PLS/ R.de.Nie -

  3. Digital Control: Pro’s and Con’s Pro’s: • No aging components determining loop behavior (BOM cost) • Adapt loop parameters on the fly: max. efficiency, non-linear control • “Native” communication with outside world: I2C, SMBus, PMBusTM • “One design fits all” (cost of ownership) • Faster design-in cycle • IC manufacturer benefits: • Big D, small a (mainstream processes, scalability) • Faster simulation, FPGA prototyping • Structural testing instead of functional testing • Less derivatives needed (programmability) Digital Control of Power / Innovation-PLS/ R.de.Nie -

  4. Digital Control: Pro’s and Con’s Con’s: • Traditional solutions for ADC, PID-controller and PWM generator are too big and power-hungry • New way of working for application engineers (GUI instead of soldering) • IC manufacturer drawbacks: • Low voltage + High voltage die’s (Multi Chip Module) • Provide GUI • Other experience needed Digital Control of Power / Innovation-PLS/ R.de.Nie -

  5. Example : Point of Load ControllerDefinition of PoL “Point of Load” is the term used for electronic devices, which: are low voltage (0.8-2.5V), high current (10-150A), DC/DC-converters are placed physically close to the load thereby minimizing self induction and power losses of the power tracks and allow circuits with different supply voltage be used on the same board Similar to VRM (Intel), but more general and less demanding • Typical load properties: • low supply voltage with tight tolerances • variable current consumption exhibiting large di/dt’s (10A-1000A/ms) Digital Control of Power / Innovation-PLS/ R.de.Nie -

  6. Example: Point of Load (PoL) POL module Digital Control of Power / Innovation-PLS/ R.de.Nie -

  7. ExampleBlock Diagram Digital PoL Controller Vin Buck Vout Vout, Vin, I_out, I_in, Temp Digital Control of Power / Innovation-PLS/ R.de.Nie -

  8. Ideally: Vout = D x Vin D is on-time duty-cycle of Control FET PIP212 “DrMOS” Control FET Sync FET Closing the LoopBasic Loop Circuit Diagram Vin Drivers Loop Controller Settings Vout PWM Fsw = 0.5 – 1 MHz Feedback Voltage mode control Digital Control of Power / Innovation-PLS/ R.de.Nie -

  9. Closing the LoopAnalog control PID controller with external R/C-filter PWM via compare to saw-tooth • Advantages • Well known • Cheap • Higher PWM frequencies not too difficult • Disadvantages • Cumbersome application (calculation feedback network, guarantee stability for all kinds of loads) • Component tolerances • Drifts over temperature and lifetime • No remote controllability Digital Control of Power / Innovation-PLS/ R.de.Nie -

  10. Vout 1cm wire 22.7mW Closing the Loopanalog transient performance with dual PIP212 + Intersil 12 us 320 mV Fsw = 500kHz dual-phase: 1 MHz eff. yellow Load step: 2V / 22.7mW = 88A di/dt ~ 33A/ms magenta green Digital Control of Power / Innovation-PLS/ R.de.Nie -

  11. (previous) error samples duty-cycle Chip boundary Coefficients Vout Digital controlADC, PID, DPWM 13-bit 10-bit General straight-forward way of implementing PID control Suitable for steady-state operation Digital Control of Power / Innovation-PLS/ R.de.Nie -

  12. Vout Digital controlADC d[n] Discrete DPWM SMPC Compensator 13-bit Ve[n] Flash ADC Sense Circuits 4-bit Vref window 12-levels Reducing necessary bit-width of ADC Digital Control of Power / Innovation-PLS/ R.de.Nie -

  13. B C A Digital controlPID controller + trunc d[n] New content 13-bit LUT-A (13x24-bit) LUT-B (13x24-bit) LUT-C (13x24-bit) reg d[n-1] (13-bit) reg Ve[n-1] (4-bit) reg Ve[n-2] (4-bit) Note: PID controller uses only 12 comparators (000-FFF) to encode errors –6 … +6 in 4 bits (0-C -> 13 values) Ve[n] 4-bit Solution for (fast) calculation of new duty-cycle Digital Control of Power / Innovation-PLS/ R.de.Nie -

  14. 2nd-order SD-modulation used, because 1st-order results in too much repetitive disturbance Digital controlDigital Pulse-Width Modulator (DPWM) Counter solution would require very high clock frequency (>1GHz) Therefore SD-modulation implemented (average duty-cycle is accurate) Digital Control of Power / Innovation-PLS/ R.de.Nie -

  15. Digital controlTransient Improvement Vout tr-mode Large signal compensator d[n] PID DPWM SMPC Compensator 13-bit Ve[n] Flash ADC Sense Circuits 4-bit Vref window 12-levels Improved transient response 15 Digital Control of Power / Innovation-PLS/ R.de.Nie - September 25, 2014

  16. Digital controlnon-linear, time-optimal • When a light-2-heavy load-step is detected by the transient detector, the high-side switch is switched on immediately • After some time the inductor current will be equal to the load current and Vout will start to rise • At the valley-point it can be calculated how much lost charge has to be made up for (shaded tri-angle). L and C have to be known • Optimal ton and toff can be determined and sequence executed, after which the control can be handed back to the PID controller Digital Control of Power / Innovation-PLS/ R.de.Nie -

  17. Digital controlnon-linear, minimum deviation • Transient detected when vout(t) (black) crosses vc-(t) or vc+(t) • At the crossings of vout(t) (black) with red curve (extreme points), iL(t) equals iload(t) • At first extreme point c(t) is extended with ton. At second extreme point c(t) kept low for toff • After toff , control can be handed back to the PID controller Digital Control of Power / Innovation-PLS/ R.de.Nie -

  18. iload(t) iL(t) L ESR Cout Digital controlnon-linear, detection circuit • When iL(t) = iload(t) : • IESR = IResr = 0 • When ESR x Cout = Resr x C*: • vc(t) becomes perfect reconstruction of intrinsic vcout(t) Digital Control of Power / Innovation-PLS/ R.de.Nie -

  19. Digital Control = Digital Power management Communication Digital Control of Power / Innovation-PLS/ R.de.Nie -

  20. Communication What can be influenced? Digital Control of Power / Innovation-PLS/ R.de.Nie -

  21. CommunicationMore parameters Digital Control of Power / Innovation-PLS/ R.de.Nie -

  22. Simulationsimulation model Vin Real_to_Float64 IC model incl. bondpads Ground <= ‘0’; Vout_ana <= real(to_integer(unsigned(Vout)))/scale_factor; REAL2PWM Digital Control of Power / Innovation-PLS/ R.de.Nie -

  23. Simulationsimulation result Looks Pretty Good PWM Vout BUT… what about real world? 30A I_ind I_load Digital Control of Power / Innovation-PLS/ R.de.Nie -

  24. Prototypingsetup Standard Altera DE2 Development board Companion board with mixed-signal part and application Digital Control of Power / Innovation-PLS/ R.de.Nie -

  25. Prototyping FPGA companion board square to pulse 12V DAC I2C PIP Flash ADC ADC Load switches + resistors analog buffers Vout 3V3 to 5V Debug Digital Control of Power / Innovation-PLS/ R.de.Nie -

  26. Prototypingreal world behavior translated to simulation When X-talk is added to the test bench simulation model, behavior looks similar Initial design behaves improperly Mainly caused by X-talk spikes induced by LX node(larger at high current) 100 MHz scope bandwidth Vout 30A I_ind Digital Control of Power / Innovation-PLS/ R.de.Nie -

  27. Prototypingresult after design has been hardened against X-talk And, when put into FPGA, real-world prototype behavior is fine as well Measures taken in IC design(NOT in application!) to counteract X-talk influence yield again a nice behavior in simulation 100 MHz scope bandwidth Digital Control of Power / Innovation-PLS/ R.de.Nie -

  28. Prototyping Response to 30A load step with and without Transient Improvement 50 ms Vout 540 mV PID only I_inductor

  29. Simulation revisitedadding X-talk in simulation model 100nF X-talk generator Vin Real_to_Float64 $bits 2real Real_to_Float64 IC model incl. bondpads Ground <= ‘0’; Vout_ana <= real(to_integer(unsigned(Vout)))/scale_factor + xtalk_real; Vout_ana <= real(to_integer(unsigned(Vout)))/scale_factor; REAL2PWM Digital Control of Power / Innovation-PLS/ R.de.Nie -

  30. Conclusions “Full” digital control can do the job ! Sticking to linear behavior will not always yield optimal performance. Sticking to “classic” digital implementations will not always yield minimum area. Use best of both worlds. FPGA prototyping will most likely reveal real-world problems early-on and gives the opportunity to fine-tune simulation models for verification. Digital Control of Power / Innovation-PLS/ R.de.Nie -

  31. QUESTIONS ? Subject / Department / Author -

  32. Literature Z. Lukic, N. Rahman and A. Prodic, “”, Multi-bit SD PWM digital controller IC for DC-DC converters operating at switching frequencies beyond 10 MHz”, IEEE Trans. Power Electronics, vol. 22, pp. 1693-1707, Sep. 2007 Zhenyu Zhao and A. Prodic, “Continuous-time digital controller for high-frequency DC-DC converters”, IEEE Trans. Power Electronics, vol. 23, pp. 564-573, Mar. 2008 A. Radic, Z. Lukic, A. Prodic and R. de Nie, “Minimum deviation digital controller IC for single and two phase DC-DC switch-mode power supplies”, in Proc. IEEE Applied Power Electronics Conf. (APEC 2010), 2010, pp. 1-6 A. Radic, A. Prodic and R. de Nie, “Self-tuning mixed-signal optimal controller with improved load transient waveform detection and smooth mode transition for DC-DC converters”, Proc. IEEE Energy Conversion Congress and Exposition (ECCE 2010) R. de Nie, “Design challenges in the development of mixed-signal control IC’s for switched-mode power supplies and their solutions”, in Proc. IEEE Workshop Comp. in Power Electronics (COMPEL 2010) Digital Control of Power / Innovation-PLS/ R.de.Nie -

  33. Subject / Department / Author -

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