Integrated Design Methodology: The Only Proven Way Nitin Deo Vice President, Product Marketing

1. Integrated Design Methodology:The Only Proven WayNitin DeoVice President, Product Marketing

2. Infrastructure Semiconductor Content Applications Enterprises Networking Equipment Services • Network processors • Switch fabric • Processors- uP- DSP- Network Proc. Small & MediumBusinesses • Microprocessors • Memories • Memory access Servers & Storage Systems Services • Multi-media • Graphics controllers • Multi-media • Mobile electronics • Low power designs Consumers PCs, Cell Phones, TVs, Set-tops Entertainment The Terabit Food Chain

3. Semiconductor Content • Processors- uP- DSP- Network Proc. • Multi-media • Graphics controllers • Low power designs The EDA Requirements • High performance designs • Structured custom techniques • Programmability • Reconfigurability • High Capacity designs • Exceeding 50 M gates today • High-end package co-design • Power sensitive designs • Multi-Vt, multi-voltage designs • Low power design techniques

4. Nanometer Design Challenges • Higher frequency (100 MHz to 1GHz) • Consumer, Mobile applications • Magma customers: NEC, Nokia, Sony • High capacity: 1 to 10M gates • Base stations, gaming, graphics • Magma users: Cisco, Broadcom, 3DLabs • Power-sensitive designs: • Multi-vt, multi-Vdd designs • Magma users: IBM, NEC, Fujitsu, STMicro • Productivity • Complexity • Performance • Signal Integrity • Power

5. Timing Constraints RTL LIB Synthesis Floorplanning STA Net List Floor plan Physical Synthesis PLIB PDEF Net List lef2plib Clock,Routing Placement iLM model LEF GDS II (lib) gds2lef GDS II Extraction STA SPEF Traditional IC design flows too complex • Series of point tools that looks at various steps • Wireload models are not useful • Corrections at the end cause iterations • Standalone analysis is dead • Power and other manufacturing effects cannot be done as point solutions • Files sizes are too big

6. Noise Analysis Power Analysis Timing Analysis RC Extraction Silicon Virtual Prototype Gain-Based Synthesis Physical Synthesis Physical Layout Magma’s Integrated Solution Integrated RTL-to-GDSII System • Merge logical & physical EDA technology • Embed high accuracy, high speed analysis engines • Eliminates massive data handling • Eliminates mismatches in timing • Streamlines IC design flow Timing Constraints GDS II .LIB RTL Single executable GDS II Fastest Design Closure

7. Magma Meets Nanometer Productivity Challenge Increased productivity while achieving total design closure INC- Incomplete

8. Blue Chip Customers

9. Magma Alliances: Foundation to Address Time-To-Market SMIC

10. From RTL to TSMC Silicon • Mutual customers: Broadcom, Vitesse, Internet Machines, PhyWorks, Sony, Hitachi, Panasonic, etc. • Strong partnership for 90nm integration Customer’s RTL and Constraints Integrated COT Methodology Fab TSMC’s Libraries and Technology Rules 0.15 um, 0.13um, 90nm

11. Why TSMC Chose Magma • “Magma can integrate TSMC process-tuned libraries with their proven EDA tools to improve faster time to volume.” - Genda Hu, VP of Marketing, TSMC • Magma worked closely with TSMC to: • Validate TSMC’s library in Magma’s design environment • Benchmark TSMC libraries • Ensure that Magma software supports TSMC manufacturing rules for 0.15m, 0.13m and 90nm • Complex design rules, via farm rules, metal rules, multi Vt cells • TSMC partnered with the industry’s best to provide high quality libraries

12. Magma ‘Ready For IBM Technology’ • Magma approved with validated Reference Flow for 0.13um and 0.18um technologies including Blast Create and Blast Fusion • Artisan libraries for 8SF and 7SF processes fully qualified • Joint customers include: 3DLabs, Vitesse, Intersil, Thomson Multi-Media, Clearspeed, etc.

13. Partnership Roadmap • Faraday is a close partner of UMC that provides: • Design services from RTL to GDS • Libraries and IPs • Tapeout services and product engineering services • Their own standard products using their own IP manufactured by UMC • Magma – Faraday/UMC partnership roadmap consists of three implementation phases • Mutual customers: Faraday, Intersil, AMCC, etc. Library Qualification LAVA Flow Adoption LAVA Flow Rollout IP Qualification IP Promotion Advanced Technology Support

14. Library data (.lib, LEF/GDS), Process Rules IP data (RTL, Timing, GDS) Hard IP Preparation Constraints Library Preparation RTL RTL Optimization Library Volcano Glassbox Check Timing ESP for Soft IP Physical Optimization Confirm Timing Physical Design GDSII Magma: The Fastest Path Complete SOC For Implementation

15. Logic Abstraction: Easy and Accurate Complex IP Integration with Glassbox Model • Physical Abstraction: Easy and Accurate Abstract • ‘True’ Timing Abstraction = Logic + Physical • Glassbox Model can be exported through IP-Lava

16. Original ARM946 Compared With Glassbox Model Original Glassbox Volcano Size: 58 MB Volcano Size: 148 MB

17. Production Use of ARM Cores Using Magma

18. Production Use of MIPS Cores Using Magma • Soft IP Implementation with ESP • Recent Silicon-proven Implementations: • NEC: CB12 (0.13um), 275 MHz • NEC: CB11 (0.18um), 234 Mhz • Infineon: C10 (0.18um), 150 MHz • TI: SR40 (0.13um), 285 MHz • Silverback: Artisan-TSMC 0.18um, 160 MHz

19. Magma: Fastest Growing EDA Company • Strong Financial Momentum • Cumulative quarterly growth over 33% • Most successful IPO of 2001 • Profitable with positive cash flows • $208M in cash • Strong market acceptance • 400+ tapeouts • More than 50 customers worldwide • 8 out of top 10 IC companies use Magma • Strong team • 285 employees worldwide • 40+ PhD’s • Large patent portfolio • R&D centers worldwide

20. Key Innovations • Patented Architecture • Unified data model enables concurrent analysis, thereby eliminating iterations • Eliminates file transfers; simplifies data management • Extensible architecture enables addition of new tools seamlessly • Patented Methodology • FixedTiming approach eliminates iterations between synthesis and P&R • Provides early predictability of achievable performance • Glassbox abstraction enables accurate modeling for hierarchical designs • Open system • Supports standard interfaces with other tools • TcL-based API enables easy access to design information

21. Cadence 10% Other 2% Cadence 24% Synopsys 64% 24% Synopsys 41% 31% The Fastest Growing Market IC Implementation Market Share • IC Implementation is RTL-to-GDSII tools • SNPS: DC + PC + Apollo • CDN: SPC + Plato • LAVA: B-RTL + B-Fusion • “This market will be one of the highest-growing markets in the next 2 years” – expected to be $483M in 2006 • Magma market share currently at 31% and growing rapidly – “grew at a staggering 343% last year” 2000 2001 Other 4% Source: Gartner Dataquest (October 2002)

22. Magma Advantage • Fast, predictable, high-capacity front end • Timing, Signal and Power Integrity solution within Implementation flow • Open system for seamless fit in your design flow • Proven to reduce TAT by 50% - 90% and development costs by 30% to 50%

23. Summary • Magma: The fastest path from RTL to Silicon • Early predictability, best QoR • Reduces TAT by 50-90% • Reduces cost by 30-50% per project • Sustained technology leadership • Clear leader at 0.18 mm and below • Ready to deliver 90 nm designs - now • Fastest growing EDA company • Strong, profitable public corporation