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Power-Aware FPGA Logic Synthesis Using Binary Decision Diagrams

Power-Aware FPGA Logic Synthesis Using Binary Decision Diagrams. Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Feb-2. Outline. Information of literature Background FPGA Design Flow

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Power-Aware FPGA Logic Synthesis Using Binary Decision Diagrams

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  1. Power-Aware FPGA Logic Synthesis Using Binary Decision Diagrams Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Feb-2

  2. Outline • Information of literature • Background • FPGA Design Flow • Logic Synthesis • Binary Decision Diagram (BDD) • Power-Aware Logic Synthesis • Comparison • Conclusion

  3. Information of literature Power-Aware FPGA Logic Synthesis Using Binary Decision Diagrams Kevin OoTinmaung, David Howland, and Russell Tessier February 2007 FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

  4. Background • Performance-oriented Design Flow • Low Power • High Speed • Methods to achieve these goals • Materials (Si,Ge have different threshold) • Devices (xMOS, FET, Bipolar) • Place and Route (longer route means larger delay) • Synthesis Algorithm • System Design (SW/HW partition)

  5. FPGA Design Flow HDL Behavioral synthesis RTL Placement RTL synthesis Routing Boolean Final Chip Logic synthesis Circuit

  6. Logic Synthesis Boolean Function Timing-Aware Area-Aware Optimization Power-Aware Mapping Circuit base on LUT

  7. Binary Decision Diagram 1/2 F=ab+cd a b Variables could be reordered. b a d c c d 1 0 1 0

  8. Binary Decision Diagram 2/2 F=ab+cd G=ab H=cd F=G+H a a c G b b d H c d 1 0 1 0 1 0 1 0

  9. Power-Aware Logic Synthesis 1/2 (1 ) (2) Transition Density (D): the average number of transitions per unit time. Static Probability (P): the probability of the signal being high for a certain time period. Lower switching activity means lower dynamic power and lower short circuit power

  10. Power-Aware Logic Synthesis 2/2 D(G) = P(G/a)*D(a) + P(G/b)*D(b) = P(b⊕0)* D(a) + P(a⊕0)* D(b) = P(b)*D(a) + P(a)*D(b) = 0.5*0.5 + 0.5*0.6 = 0.55 P(G) = P(a=1,b=1) = P(a)*P(b) = 0.5*0.5 = 0.25

  11. Comparison

  12. Conclusion • Power-aware BDD based Synthesis Algorithm could reduce power consumption. • Power-aware BDD based Synthesis Algorithm may causeincrease timing delay. • Proposed method could be useful in low power design.

  13. Question Thanks!

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