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Activities of the TUB

HW-SW co-design UML based code generation for embedded systems Fault-tolerant system design - WDP Hardware synthesis Logic minimization FPGA based DSP Pilot projects. Testing Adaptation of the BUDATEST tool for IDDQ testing Information technology

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Activities of the TUB

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  1. HW-SW co-design UML based code generation for embedded systems Fault-tolerant system design - WDP Hardware synthesis Logic minimization FPGA based DSP Pilot projects Testing Adaptation of the BUDATEST tool for IDDQ testing Information technology WWW based cooperative design/teaching(Lotus Notes) Information dissemination Activities of the TUB

  2. Testing • BUDATEST • CSP based high-level test generator tool (FUTEG) • VHDL RT description • Component tests • IDQQ testing by scenario based tests • Currently: SW engineering • Expected: 1999.IV.

  3. Watch-dog processor • simple coprocessor • control flow checking • assigned signatures • SEIS methodology (EDCC1) • VHDL description  • Industrial use (?) : Russia, VxWorks (EDCC3)

  4. UML: evolving standard Very broad scope Visual notation Standard semantics Easy-to understand Broad industrial support Notation+methodology Formal verification Variety of tools Applicability for the in-the small end? Static model hierarchical refinement class diagram inheritance Dynamic model Statechart(internal behavior) sequence diagram (interaction with the environment) activity diagram UML based code generation

  5. on off on image off standby txt show videotxt txt off on on sound mute/txt disconnected sound_on sound_off out sound Statechart

  6. UML model Innovator Code generation HIDE technology Database Oracle Tcl/Tk PL/SQL PIC assembly MPLAB PL/SQL ISR_START: MOVF EVENT_QUEUE_WRITE_PTR,W XORLW 0X37 BTFSS STATUS,Z GOTO WQ_NOT_ROUNDED WQ_ROUNDED: MOVLW 0X30 MOVWF EVENT_QUEUE_WRITE_PTR GOTO WQ_NOT_ROUNDED_END

  7. The target architecture Well supported PIC 16C73A RISC (Harvard architecture) 2k word x13 bit instructions (ROM) 96 byte data (RAM) Run-time system Main cycle (”kernel”) Event queue Events, sent by: Ext., int. interrupts State transitions Transitions, actions and guards Implementation

  8. State (statechart) based design Easy-to-understand modeling:redundancy Hardware design:compactness Fast algorithms Integration planned Comparisons initiated Core algorithm as a stand-alone PASCAL program Decision upon integration:after the experiences Heuristic logic minimization

  9. FPGA based design low to medium production series HW: compactness Fast algorithms for structural minimization Algorithmic optimization: Spatial/temporal Operator reordering FIR structures MATLAB Interfaces to FPGA tools Experiments: XILINX based FPGA based DSP

  10. Standard technology Good protection system Support for: documentation handling workflow management version control web based Information dissemination Cooperation Automatic processes (agents) Lotus Notes (non-VILAB sources) Teaching: LearningSpace Information technology

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