Logic Design of Digital Systems Lecture 8: Analysis of Combinational Systems

W’05 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital SystemsLecture 8 February 7 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200

Outline • Administrative Matter • Review: Design of combinational systems • Chapter 4: Analysis of combinational systems • Summary

Administrative Matter • Quiz #2 • Will be handed back on Wednesday • Project #1 • Will be assigned on Wednesday • Class Grade • Will be available via myUCLA gradebook

Specification Implementation Design Design of Comb. Systems - Big Picture • Minimization • Boolean Algebra • K-Map • Quine-McCluskey Algorithm • Truth Table • Switching Expression • K-Map • VHDL • Timing Diagram • Logic Diagram • Net List • Two-Level Logic • AND-OR, OR-AND • NAND-NAND, NOR-NOR • Multi-Level Logic • XORs • Programmable Modules • PLAs • PALs

Implementation Specification Analysis Analysis of Comb. Systems - Big Picture • Analysis: • Given a gate network of a system, find what the system does (binary level and high-level). • Objectives: • Verify the system’s function • Debug the implementation • Optimize the system implementation

Questions that Analysis Tries to Address • Validity analysis • Is the implementation a valid combinational gate network? • Functional analysis • What does the network do? • Binary-level  switching function • High-level  meaningful statement • Performance analysis • How fast/well does the network perform? • Delays, fanout factors, input load factors • Cost analysis • How much does it take to perform so? • Network size • Power dissipation, etc.

Validity Analysis • A gate network: • A network that implements a combinational system. • Consists of • Logic gates • Connections • External inputs/outputs (primary inputs/outputs)

Validity Analysis - Criteria • Each gate input has to be connected to a stable signal source (0, 1, etc.) • No “floating wires” • How to deal with don’t cares? • Multiple sources of an input (“Wired-OR”) are not allowed

Validity Analysis - Criteria (Cont’d) • A gate must not be overloaded • The output load imposed on a gate output should be less than its fan-out factor • Gates in a gate network must be electrically compatible • All gates belong to the same logic family

Validity Analysis - Criteria (Cont’d) • No loop is allowed • It is not possible to pass an input of a gate twice from any paths Not a Combinational network! A valid Combinational network!

Universal Set • {AND, OR, NOT} • {NAND} • {NOR} • {AND, NOT} • {OR, NOT}

Functional Analysis • Typical Statement: • Given the diagram of a gate network, what is its function? • Binary-Level: yi = fi (xj) and fi = ? • High-Level: • Basic Procedure: • Step 1. Obtain switching expressions of the network outputs in terms of network inputs • Step 2. Find the truth table of the network outputs • Step 3. Define high-level input and output variables and use the same encoding scheme • Step 4. Find the high-level specifications

Step 1: Obtain Switching Expressions • Divide the gate network into several levels of subsystems (modules) in case of a complex network • Introduce some intermediate (internal) inputs and outputs for each module • Write the switching expression (s) for each module • Work backwards to replace each intermediate (internal) variables until get the relationship expression of network outputs in terms of network inputs

Step 1: Example 1

Functional Analysis - Some Tips • Use Divide-and-Conquer Approach • Decompose the network into simple subsystems (modules) • Analyze each subsystem separately • Use replacement to obtain the network functions • Partition along data flow • From inputs to outputs • Start from outputs and work backwards • Backwards analysis generally is more effective • “Bubble Logic” is useful for negation-rich gate networks • NOT, NAND, NOR networks • Many arithmetic modules are implemented in bit-slice style

Functional Analysis - Example 2

Binary-Level: High-Level: Example 2 (Cont’d)

Binary-Level: Example 2 (Cont’d)

Truth Table: Functional Table: High-Level Spec: Final High-Level Spec: Example 2 (Cont’d)

Example 3 - “Bubble Logic” in Action • Basic Ideas: • Remove a negation (complementation), or • Produce two negations in a connection so that they can cancel each other. • Basic Rules: • Apply “bubble logic” in every other level, starting from the output.

Level 3 Level 1 Switching Expression: Example 3 (Cont’d)

Level 3 Level 1 Functional Analysis - Example 4

Example 4 (Cont’d)

Performance (Timing) Analysis • Typical Statement: • Given an implementation, find out the propagation delays TpLH and TpHL • Basic Procedure: • Step 1. Find out the critical path of the gate network • Step 2. Decide the transition direction of each gate on the critical path, starting from the output backwards • Step 3. Write the expression for the total delay in terms of delays in individual gates • Step 4. Look up the gate characteristics table and plug in the values

Timing Analysis - Some Concepts • Load factor of a network input • Fan-out factor of a network output • Size of the network • Number of levels of a network • Critical path of the network • The network (propagation) delay

Characteristics of a CMOS Gate Family

Timing Analysis - Example 5 Load Factors: all = 1 Fan-out Factors: For z2 and z1: 12 For z0: 12-2 = 10 Network Size: 21 actual gates 38 equivalent gates

Example 5 (Cont’d) The Critical Path: - number of gates: level - types of gates - fan-ins O1->N1->A2->O2->N2->A9->O5 Is the brown path a critical path? The number of levels: 7

HL LH LH LH HL HL HL Example 5 (Cont’d) LH HL HL Transition Direction: HL LH LH LH

Network (Propagation) Delays: Example 5 (Cont’d)

Example 5 (Cont’d) Network (Propagation) Delays:

Summary • Analysis of combinational gate networks • Validity analysis • Functional analysis • Performance analysis

Next Lecture • Chapter 10 – Computer Arithmetic • VHDL Primer

Logic Design of Digital Systems Lecture 8: Analysis of Combinational Systems