EE534 VLSI Design System Summer 2004 Lecture 7: Static Dynamic CMOS inverter (CHAPTER 6)

1. EE534VLSI Design SystemSummer 2004 Lecture 7: Static Dynamic CMOS inverter (CHAPTER 6)

2. Calculation of Delay times: Average current method The average current during high to low transition can be calculated by using the current values at the beginning and the end of the transition. The average current during low to high transition can be calculated by using the current values at the beginning and the end of the transition.

3. Review: Inverter delay, falling • Total fall delay =(t1-t0) + (t2-t1)

4. Review: Inverter delay, rising • Similar calculation as for falling delay • Separate into regions where PMOS is in linear, saturation

5. Review: CMOS inverter actual delay • What if input has finite rise/fall time?not a step pulse • Both transistors are on for some amount of time • Capacitor charge/discharge current is reduced Empirical equations:

6. Review: Propagation delay simulation results At very short channel width, the delay approaches a limit value of about 0.2nsec , which is mainly determined by technology-specific parameters, independent of extrinsic capacitance component.

7. Review: Inverter delay revisited (Lower Vdd Increases Delay)

8. CMOS Ring Oscillator Circuit

9. CMOS Ring Oscillator Circuit (cont.) T=PHL1+PLH1+ PHL2+PLH2+ PHL3+PLH3 =2 P+ 2P+ 2P =6P

10. Calculation of interconnect delay: Switch-level model(RC delay model) • Model transistors as switches and resistances • Resistance Ron = average resistance for a transition • For NMOS tphl: RP A Rn CL A

11. Switch-level model Delay estimation using switch-level model (for general RC circuit): Rn CL

12. Propagation delay of simple lumped RC network • For fall delay tphl, V0=Vcc, V1=Vcc/2 Standard RC-delay equations

13. Interconnect delay – Elmore Delay • For long interconnect lines, RC must be distributed to obtain accurate simulation results • Elmore Delay – first order time constant • simple, close approximation of delay

14. Interconnect Resistance • Resistance is proportional to cross-sectional area • As interconnect scales, increase aspect ratio to maintain same area.

16. Review: Designing Inverters for Performance • Reduce CL • internal diffusion capacitance of the gate itself • interconnect capacitance • fanout • Increase W/L ratio of the transistor • the most powerful and effective performance optimization tool in the hands of the designer • Increase VDD • only minimal improvement in performance at the cost of increased energy dissipation • Slope engineering - keeping signal rise and fall times smaller than or equal to the gate propagation delays and of approximately equal values • good for performance • good for power consumption

17. CMOS inverter Power Dissipation

18. Why worry about power? -- Power Dissipation Lead microprocessors power continues to increase 100 P6 Pentium ® 10 486 286 8086 Power (Watts) 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Power delivery and dissipation will be prohibitive Source: Borkar, De Intel

19. 10000 1000 Rocket Sun’s …chips might become hot… Nozzle Surface 100 Nuclear Power Density (W/cm2) Reactor 8086 10 4004 P6 Hot Plate 8008 Pentium® 8085 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Why worry about power? -- ChipPower Density Source: Borkar, De Intel

20. On-Die Temperature Chip Power Density Distribution Power Map • Power density is not uniformly distributed across the chip • Silicon is not a good heat conductor • Max junction temperature is determined by hot-spots • Impact on packaging, w.r.t. cooling

21. CMOS inverter power • Power has three components • Static power: when input isn’t switching • Dynamic capacitive power: due to charging and discharging of load capacitance • Dynamic short-circuit power: direct current from VDD to Gnd when both transistors are on

22. CMOS inverter static power • Static power consumption: • Static current: in CMOS there is no static current as long as Vin < VTN or Vin > VDD+VTP • Leakage current: determined by “off” transistor • Influenced by transistor width, supply voltage, transistor threshold voltages VDD VDD Ileak,p VDD VI<VTN Vo(low) Vcc Ileak,n

23. Drain junction leakage Sub-threshold current Gate leakage Leakage (Static) Power Consumption VDD Ileakage Vout Sub-threshold current is the dominant factor. All increase exponentially with temperature!

24. Leakage as a Function of VT • Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthreshold conduction a dominate component of power dissipation. 10-2 • An 90mV/decade VT roll-off - so each 255mV increase in VT gives 3 orders of magnitude reduction in leakage (but adversely affects performance) 10-7 10-12

25. Exponential Increase in Leakage Currents Ileakage(nA/m) Temp(C) From De,1999

26. Dynamic Power Consumption Vdd Vin Vout CL

27. Dynamic Capacitive Power and energy stored in the PMOS device Case I: When the input is at logic 0: Under this condition the PMOS is conducting and NMOS is in cutoff mode and the load capacitor must be charged through the PMOS device. Power dissipation in the PMOS transistor is given by, PP=iLVSD= iL(VDD-VO) The current and output voltages are related by, iL=CLdvO/dt Similarly the energy dissipation in the PMOS device can be written as the output switches from low to high , Above equation showed the energy stored in the capacitor CL when the output is high.

28. Power Dissipation and Total Energy Stored in the CMOS Device Case II: when the input is high and out put is low: During switching all the energy stored in the load capacitor is dissipated in the NMOS device because NMOS is conducting and PMOS is in cutoff mode. The energy dissipated in the NMOS inverter can be written as, The total energy dissipated during one switching cycle is, The power dissipated in terms of frequency can be written as This implied that the power dissipation in the CMOS inverter is directly proportional to switching frequency and VDD2

29. Dynamic capacitive power • Formula for dynamic power: • Observations • Does not (directly) depend on device sizes • Does not depend on switching delay • Applies to general CMOS gate in which: • Switched capacitances are lumped into CL • Output swings from Gnd to VDD • Input signal approximated as step function • Gate switches with frequency f Not a function of transistor sizes! Data dependent - a function of switching activity!

30. Capacitance: Function of fan-out, wire length, transistor sizes Supply Voltage: Has been dropping with successive generations Clock frequency: Increasing… Lowering Dynamic Power Pdyn = CL VDD2f

31. Short Circuit Power Consumption Vin Isc Vout CL Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting.

32. Dynamic short-circuit power • Short-circuit current flows from VDD to Gnd when both transistors are on • Plot on VTC curve: Imax: depends on saturation current of devices VCC Imax Vout ID Vin VCC

33. Dynamic short-circuit power • Approximate short-circuit current as a triangular wave • Energy per cycle: Imax

34. Short Circuit Currents Determinates • Duration and slope of the input signal, tsc • Ipeak determined by • the saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc. • strong function of the ratio between input and output slopes • a function of CL Psc = tsc VDD Ipeak f01

35. Isc  0 Isc  Imax Impact of CL on Psc Vin Vout Vin Vout CL CL Large capacitive load Output fall time significantly larger than input rise time. Small capacitive load Output fall time substantially smaller than the input rise time.

36. Ipeak as a Function of CL x 10-4 When load capacitance is small, Ipeak is large. CL = 20 fF CL = 100 fF Ipeak (A) Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering. CL = 500 fF x 10-10 time (sec) 500 psec input slope

37. Psc as a Function of Rise/Fall Times When load capacitance is small (tsin/tsout > 2 for VDD > 2V) the power is dominated by Psc VDD= 3.3 V P normalized VDD = 2.5 V If VDD < VTn + |VTp| then Psc is eliminated since both devices are never on at the same time. VDD = 1.5V tsin/tsout W/Lp = 1.125 m/0.25 m W/Ln = 0.375 m/0.25 m CL = 30 fF normalized wrt zero input rise-time dissipation

38. Inverter power consumption • Total power consumption

39. Power reduction • Reducing dynamic capacitive power: • Lower the voltage (Vdd)! • Quadratic effect on dynamic power • Reduce capacitance • Short interconnect lengths • Drive small gate load (small gates, small fan-out) • Reduce frequency • Lower clock frequency - • Lower signal activity

40. Power reduction • Reducing dynamic capacitive power: • Lower the voltage (Vdd)! • Quadratic effect on dynamic power • Reduce capacitance • Short interconnect lengths • Drive small gate load (small gates, small fan-out) • Reduce frequency • Lower clock frequency - • Lower signal activity

41. Power reduction • Reducing dynamic capacitive power: • Lower the voltage (VDD) • Quadratic effect on dynamic power • Reduce capacitance • Short interconnect lengths • Drive small gate load (small gates, small fan-out) • Reduce frequency • Lower clock frequency - • Lower signal activity

42. Examples f=500MHz CL=15fF/gate VDD=2.5V Pdyn=50W For a design with I million gate Pdyn=50W! Is this possible in reality? If not why? Pdyn=Edyn/2tp=580W for tp=32.5ps Pdyn=Edyn/2tp=155W for f=4GHz(250ps)

43. Power reduction • Reducing short-circuit current: • Fast rise/fall times on input signal • Reduce input capacitance • Insert small buffers to “clean up” slow input signals before sending to large gate • Reducing leakage current: • Small transistors (leakage proportional to width) • Lower voltage

44. (Lower-power and Robust) Good Fast Cheap (Short Delay) (Small Layout) Retrospect on Design Trade-offs • Design trade-offs dance around the triangle, but still important • Fundamental improvement that shrinks the triangle: • Scaling in technology (lithography improvement) • New functionality • New architecture • New algorithms