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A. J. Ginés*, R. Doldán, A. Rueda and E. Peralías

POWER OPTIMIZATION OF CMOS PROGRAMMABLE GAIN AMPLIFIERS WITH HIGH DYNAMIC RANGE AND COMMON-MODE FEED-FORWARD CIRCUIT. A. J. Ginés*, R. Doldán, A. Rueda and E. Peralías Instituto de Microelectrónica de Sevilla (CNM-CSIC) University of Seville (Spain). IEEE ICECS 2010. Contents. Motivations

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A. J. Ginés*, R. Doldán, A. Rueda and E. Peralías

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  1. POWER OPTIMIZATION OF CMOS PROGRAMMABLE GAIN AMPLIFIERS WITH HIGH DYNAMIC RANGE AND COMMON-MODE FEED-FORWARD CIRCUIT A. J. Ginés*, R. Doldán, A. Rueda and E. Peralías Instituto de Microelectrónica de Sevilla (CNM-CSIC)University of Seville (Spain) IEEE ICECS 2010

  2. Contents • Motivations • State-of-the-Art in Low Voltage PGAs • Close-loop vs. Open-loop Architectures • Proposed PGA Architecture • Design Methodology • Common-Mode Feed-forward Circuit (CMFFC) • Verification: • Post-layout Simulation Results (3-stage PGA) • Experimental Results (stage core) • Conclusions

  3. Motivations • Low-IF ZigBee Receiver • ZigBee should operate with power levels at the antenna from -85dBm to -20dBm (DR > 64dB). • Adjustable gain through the chain is need to optimize the sensitivity and signal-to-noise ratio (SNR). • Power consumption is one of the most critical design constraints in ZigBee standard. 1

  4. Motivations • Low-IF ZigBee Receiver This Work • ZigBee should operate with power levels at the antenna from -85dBm to -20dBm (DR > 64dB). • Adjustable gain through the chain is need to optimize the sensitivity and signal-to-noise ratio (SNR). • Power consumption is one of the most critical design constraints in ZigBee standard. 1

  5. Contents • Motivations • State-of-the-Art in Low Voltage PGAs • Close-loop vs. Open-loop Architectures • Proposed PGA Architecture • Design Methodology • Common-Mode Feed-forward Circuit (CMFFC) • Verification: • Post-layout Simulation Results (3-stage PGA) • Experimental Results (stage core) • Conclusions

  6. State-of-the-Art in Low Voltage PGAs • Close-loop Architectures G = Rf / Rin 2

  7. State-of-the-Art in Low Voltage PGAs • Close-loop Architectures • Take advantage of resistive feedback to achieve: • High Linearity • Low Noise G = Rf / Rin 2

  8. State-of-the-Art in Low Voltage PGAs • Close-loop Architectures • Take advantage of resistive feedback to achieve: • High Linearity • Low Noise • Drawbacks of the classical approach: • Gain programmability introduces stability issues. • Low voltage limitations due to equal common modes (cmi = cmo). • Buffers are required to deal with low input impedance. G = Rf / Rin 2

  9. State-of-the-Art in Low Voltage PGAs • Close-loop Architectures • Take advantage of resistive feedback to achieve: • High Linearity • Low Noise • Drawbacks of the classical approach: • Gain programmability introduces stability issues. • Low voltage limitations due to equal common modes (cmi = cmo). • Buffers are required to deal with low input impedance. G = Rf / Rin Current Division Network (CDN) Reference: [3] 2

  10. State-of-the-Art in Low Voltage PGAs • Close-loop Architectures • Take advantage of resistive feedback to achieve: • High Linearity • Low Noise • Drawbacks of the classical approach: • Gain programmability introduces stability issues. • Low voltage limitations due to equal common modes (cmi = cmo). • Buffers are required to deal with low input impedance. G = Rf / Rin Decoupling common mode (cmi ≠ cmo) Reference: [4] 2

  11. State-of-the-Art in Low Voltage PGAs • Close-loop Architectures • Take advantage of resistive feedback to achieve: • High Linearity • Low Noise • Drawbacks of the classical approach: • Gain programmability introduces stability issues. • Low voltage limitations due to equal common modes (cmi = cmo). • Buffers are required to deal with low input impedance. G = Rf / Rin Transimpedance amplifier Reference: [6] 2

  12. State-of-the-Art in Low Voltage PGAs • Close-loop Architectures • Take advantage of resistive feedback to achieve: • High Linearity • Low Noise G = Rf / Rin • Main drawback for ZigBee: • High power consumption is required for driving resistive load. • It does not take advantage of the standard linearity relaxation. Solution: Open-loop topologies !!! 2

  13. State-of-the-Art in Low Voltage PGAs • Open-loop Architectures G = gmRo 3

  14. State-of-the-Art in Low Voltage PGAs • Open-loop Architectures • Advantages: • High-speed and high-stability • Low-Power G = gmRo Gilbert’s Cell References: [8-10] 3

  15. State-of-the-Art in Low Voltage PGAs • Open-loop Architectures • Advantages: • High-speed and high-stability • Low-Power • Drawbacks: • Gain is not accurately defined. • Low-voltage operation. • Non-linearity G = gmRo Gilbert’s Cell References: [8-10] 3

  16. State-of-the-Art in Low Voltage PGAs • Open-loop Architectures • Advantages: • High-speed and high-stability • Low-Power • Drawbacks: • Gain is not accurately defined. • Low-voltage operation. • Non-linearity G = gmRo Gilbert’s Cell References: [8-10] 3

  17. State-of-the-Art in Low Voltage PGAs • Open-loop Architectures • Advantages: • High-speed and high-stability • Low-Power • Drawbacks: • Gain is not accurately defined. • Low-voltage operation. • Non-linearity G = gmRo Gilbert’s Cell References: [8-10] 3

  18. State-of-the-Art in Low Voltage PGAs • Open-loop Architectures with Feed-back Resistive degeneration enhances linearity 4

  19. State-of-the-Art in Low Voltage PGAs • Open-loop Architectures with Feed-back Resistive degeneration enhances linearity Further Improvement This Work References: [18-22] Gain Boosting Servo-loop [20,21] Super-Source Follower (SSF) [18,19] 4

  20. Contents • Motivations • State-of-the-Art in Low Voltage PGAs • Close-loop vs. Open-loop Architectures • Proposed PGA Architecture • Design Methodology • Common-Mode Feed-forward Circuit (CMFFC) • Verification: • Post-layout Simulation Results (3-stage PGA) • Experimental Results (stage core) • Conclusions

  21. Proposed Low Power PGA Architecture • A 1.2V 72dB 3-stage PGA in 90nm CMOS process 5

  22. Proposed Low Power PGA Architecture • A 1.2V 72dB 3-stage PGA in 90nm CMOS process 5

  23. Proposed Low Power PGA Architecture • A 1.2V 72dB 3-stage PGA in 90nm CMOS process How much currents in 90nm CMOS? Stress due to trench isolation barriers!!! 5

  24. Proposed Low Power PGA Architecture • A 1.2V 72dB 3-stage PGA in 90nm CMOS process How much currents in 90nm CMOS? Stress due to trench isolation barriers!!! All the transistors have the same width, length and number of fingers. The only difference is the multiplicity. 5

  25. Proposed Low Power PGA Architecture • A 1.2V 72dB 3-stage PGA in 90nm CMOS process Gain Poles Zero 5

  26. Proposed Low Power PGA Architecture • Design Methodology Specifications G BW Power THD OS Noise VDD Ib C0ω2 6

  27. Proposed Low Power PGA Architecture • Design Methodology Specifications G BW Power THD OS Noise VDD Ib C0ω2 Initial guess cmo, cmi 6

  28. Proposed Low Power PGA Architecture • Design Methodology Specifications G BW Power THD OS Noise VDD Ib C0ω2 Initial guess Formulae BW, C0 R0 cmo, cmi cmo, R0 F5 6

  29. Proposed Low Power PGA Architecture • Design Methodology Specifications G BW Power THD OS Noise VDD Ib C0ω2 Initial guess Formulae Formulae Pick Values G, ω2 F3 BW, C0 R0 Fs=R0/RS FN cmo, cmi W1, W5, W4, WBP, WBN cmo, R0 F5 OP-AC Simulation NO BW, Noise ? 6

  30. Proposed Low Power PGA Architecture • Design Methodology Specifications G BW Power THD OS Noise VDD Ib C0ω2 Initial guess Formulae Formulae Pick Values G, ω2 F3 BW, C0 R0 Fs=R0/RS FN cmo, cmi W1, W5, W4, WBP, WBN cmo, R0 F5 OP-AC Simulation NO NO BW, Noise ? YES PSS Simulation END THD, Power ? YES 6

  31. Proposed Low Power PGA Architecture • Key Aspects in the Design 7

  32. Proposed Low Power PGA Architecture • Key Aspects in the Design 1.- AC-coupling 2.- CMFF Circuit 7

  33. Proposed Low Power PGA Architecture • Key Aspects in the Design 1.- AC-coupling 2.- CMFF Circuit AC-coupling 7

  34. Proposed Low Power PGA Architecture • Key Aspects in the Design 1.- AC-coupling 2.- CMFF Circuit AC-coupling • Traditional assumptions for PGAs, such as the convenience of DC-coupling [1], must be revised in a low-voltage high-dynamic range scenario S = 2 (Vinpmax- Voutpmin) ≈ 0.28Vpp S = 2 (Vinp,outpmax- Vinp,outpmin) > 0.90Vpp VDD/2 0.4 0.4 DC-coupled AC-coupled 0.2 0.2 -0.2 Voltage Range (V) -0.2 Voltage Range (V) 7

  35. Proposed Low Power PGA Architecture • Key Aspects in the Design 1.- AC-coupling 2.- CMFF Circuit AC-coupling • Traditional assumptions for PGAs, such as the convenience of DC-coupling [1], must be revised in a low-voltage high-dynamic range scenario S = 2 (Vinpmax- Voutpmin) ≈ 0.28Vpp S = 2 (Vinp,outpmax- Vinp,outpmin) > 0.90Vpp VDD/2 • Advantages: • Different cmi and cmo • Greater dynamic range • High linearity without resistive feedback • Low-power consumption 0.4 0.4 DC-coupled AC-coupled 0.2 0.2 -0.2 Voltage Range (V) -0.2 Voltage Range (V) 7

  36. Proposed Low Power PGA Architecture • Key Aspects in the Design 1.- AC-coupling 2.- CMFF Circuit 8

  37. Proposed Low Power PGA Architecture • Key Aspects in the Design Common-Mode Feed-forward Circuit (CMFF) 8

  38. Proposed Low Power PGA Architecture • Key Aspects in the Design Common-Mode Feed-forward Circuit (CMFF) ( common for all stage) 8

  39. Proposed Low Power PGA Architecture • Key Aspects in the Design Common-Mode Feed-forward Circuit (CMFF) • Advantages: • Common-mode feedback circuit can be suppressed since relatively low impedance is found at the output (Ro is usually in the order of k). • Low-cost low-power solution. • Accurately definition of the output common-mode (cmo). • Functionality guaranteed with Corners and Monte-Carlo simulations. ( common for all stage) 8

  40. Contents • Motivations • State-of-the-Art in Low Voltage PGAs • Close-loop vs. Open-loop Architectures • Proposed PGA Architecture • Design Methodology • Common-Mode Feed-forward Circuit (CMFFC) • Verification: • Post-layout Simulation Results (3-stage PGA) • Experimental Results (stage core) • Conclusions

  41. Verification: 3-stage PGA • Target Specifications • Gain = 0 to 72dB in 6-dB steps • Bandwidth > 15MHz • ω 2 >> BW • Power < 2.5mW • Input referred noise (Gmax) < 15nVrms /Hz • THD (Gmax) < -36dB • Vdd = 1.2V  5% 9

  42. Verification: 3-stage PGA • Post-layout Simulation Results (90nm CMOS) Active Section 65µm 3-stg PGA Decoupling Network 165µm STG Layout Stage-core 110µm 9

  43. Verification: 3-stage PGA • Corners and Monte-Carlo Specifications (Post-layout) 10

  44. Verification: 3-stage PGA • Corners and Monte-Carlo Specifications (Post-layout) 10

  45. Verification: 3-stage PGA • Corners and Monte-Carlo Specifications (Post-layout) 10

  46. Verification (not included in the paper) • Experimental Results (single stage) Gain ↑ PCB Test Setup + HP3589A Analyzer Simulated: - - Measured: ― Single-to-Differential Input Buffers & Diff.-to-Single Output Buffers This work has been partially supported by the Spanish projects TEC2007-68072 and P09-TIC-5386, and by the Catrene European project SR2 2A105 (all co-founded by FEDER). 11

  47. Verification (not included in the paper) • Experimental Results (single stage) PCB Test Setup + HP3589A Analyzer Single-to-Differential Input Buffers & Diff.-to-Single Output Buffers This work has been partially supported by the Spanish projects TEC2007-68072 and P09-TIC-5386, and by the Catrene European project SR2 2A105 (all co-founded by FEDER). 11

  48. Contents • Motivations • State-of-the-Art in Low Voltage PGAs • Close-loop vs. Open-loop Architectures • Proposed PGA Architecture • Design Methodology • Common-Mode Feed-forward Circuit (CMFFC) • Verification: • Post-layout Simulation Results (3-stage PGA) • Experimental Results (stage core) • Conclusions

  49. Conclusions • In this paper, we have shown that open-loop topologies with gain boosting present an optimum trade-off between power consumption and linearity for ZigBee applications. • We have proposed a design methodology for low-voltage PGAs with resistive degeneration. • The developed design flow is shown with a 1.2V 72dB 1.95mW PGA implementation in a TSMC 90nm CMOS process. • Power optimization is improved thanks to the use of a front-end capacitive decoupling network and a common-mode feed-forward circuit shared between all stages. • The front-end capacitive decoupling network also improves the PGA dynamic range. Actually, a THD < -42dB is achieved for a 1.2Vpp output excursion, G = {4,8,16}. 12

  50. POWER OPTIMIZATION OF CMOS PROGRAMMABLE GAIN AMPLIFIERS WITH HIGH DYNAMIC RANGE AND COMMON-MODE FEED-FORWARD CIRCUIT Thank you very much for your attendance Questions? A. J. Ginés, Email: gines@imse-cnm.csic.es Instituto de Microelectrónica de Sevilla (CNM-CSIC)University of Seville (Spain)

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