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ET4508/ED5532: Computer Systems Architecture

ET4508/ED5532: Computer Systems Architecture. Lecturer: Dr. Karl Rinne. Contact. Dr. Karl Rinne Room: F2-021 (moving…) ER2-018 (from 21/02/2005 on) Extension: 2309 Email: karl.rinne@ul.ie Web: http://www.ul.ie/~rinne. Please note…. Please pre-arrange all meetings

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ET4508/ED5532: Computer Systems Architecture

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  1. ET4508/ED5532: Computer SystemsArchitecture Lecturer: Dr. Karl Rinne

  2. Contact • Dr. Karl Rinne • Room: F2-021 (moving…) ER2-018 (from 21/02/2005 on) • Extension: 2309 • Email: karl.rinne@ul.ie • Web: http://www.ul.ie/~rinne KR

  3. Please note… • Please pre-arrange all meetings • email karl.rinne@ul.ie • Regularly check the web • visit http://www.ul.ie/~rinne • latest announcements • additional exercises • etc KR

  4. Please note… • This is a lecture dealing mainly with computer architectures / computer hardware • pace is fast, material is interesting and demanding • we’ll look at software only sporadically - whenever necessary… (x86 assembler or C Code fragments) • Interactive lectures • if you have any question, interrupt anytime… KR

  5. Please note… • Exercises will be given • in the lecture notes • on the web • during class • Take the time to study & solve exercises! • Tutorials for weeks 8-12 will be arranged if required KR

  6. Please note… • Lab(s) will be arranged to give you hands-on PC hardware experience • Lab(s) will take place from week 6 • Can be completed • Lab report including post-lab research KR

  7. Please note… • Try to attend all lectures! • Lecture will deviate somewhat from lecture notes • (Exam-relevant) exercises will be given and discussed • Lecture notes • very comprehensive • available in print room shortly (availability will be announced) • Complete lecture material (notes, slides, labs, assignment, exam papers, etc) is available online (www.ul.ie/~rinne/et4508.htm) KR

  8. Please note • Course pre-requisites • Basics of digital systems, digital primitives • Boolean algebra, combinational and sequential logic, gates, FFs, truth tables, timing diagrams, etc. • Computer number systems • decimal, hexadecimal, binary • conversions, logical operations, arithmetics • Computer data formats • ascii, bcd KR

  9. Grading and Exam • Grading • Final Term Exam: 80% • Lab + Post-lab research + report: 20% • Lab report due end of week 8 (Fri, 11am) KR

  10. Spring 2005 Special Announcement • Student services requested a change of classroom (for the duration of the semester) • D1-050C2-062 KR

  11. Aims of the course • See how processors have evolved • Become familiar with the Intel x86 Architecture, from 8086 to P4 • Become familiar with the Hardware Elements of a PC • Understand the directions in which PCs may evolve • Obtain some hands-on PC hardware experience KR

  12. Quotes… • “DOS addresses only 1 MB of RAM because we cannot imagine any applications needing more.”Microsoft, 1980 • “I don’t think it’s that significant”Tandy president John Roach on the IBM PC KR

  13. Questions… • What exactly is a PC? KR

  14. Questions… • What exactly is a PC? IBM PC 1981 Apple I 1976 Sinclair ZX80 1980 Apple Mac 1984 Atari 400 1979 KR

  15. Questions… • Who invented the PC? • Who controls the PC standards today? KR

  16. Course Outline (1) • Review Microprocessor Fundamentals • MPU Register set and Internal Architecture • MPU buses • Memory Considerations • MPU interfacing: Interrupts and DMA • Intel x86 Architecture • CISC vs RISC • Memory and Computer Performance KR

  17. Course Outline (2) • PC Architecture: Processor, Memory, Buses, I/O, Relevance to BIOS • PCI, ISA, PC Card, PC 104 and other interface standards • Serial and parallel interfaces (legacy to status quo) KR

  18. Text Books • Upgrading and Repairing PCs, Scott Mueller. Que 2000. ISBN: 0-7897-2542-8 • The Indispensable PC Hardware Book, Hans-Peter Messmer. Addison Wesley Longman 1997. ISBN 0-201-40399-4 • Computer Systems Architecture, A Networking Approach. Addison Wesley 2000. ISBN 0-201-64859-8 • Digital Fundamentals, Floyd (8086 Section) KR

  19. Other Good References • The Intel Microprocessors: 8086 … Pentium Pro Processor, Barry B Brey (5th Edition), Prentice Hall 1997 • PC Support Handbook • Bigelow’s book on PC Maintenance • Microprocessor Architecures, Steve Heath KR

  20. Useful Web-sites • Intel Home: www.intel.com • Intel Processor page: http://developer.intel.com/design/processor/ • Intel Processor Hall of Fame: http://www.intel.com/intel/museum/25anniv/hof/hof_main.htm • Intel Processor Specs: http://www.intel.com/intel/museum/25anniv/hof/tspecs.htm • The Intel Museum: http://intel.com/intel/intelis/museum/ KR

  21. Useful Web Sites (2) • How Microprocessors Work: http://intel.com/education/mpuworks/index.htm • Intel Processor Quick Reference: http://www.intel.com/pressroom/kits/processors/quickref.htm • Intel Developer Home: http://developer.intel.com/ • Intel Pentium II: http://developer.intel.com/design/PentiumII/ • Intel Pentium III: http://developer.intel.com/design/PentiumIII/ • Intel Pentium 4: http://developer.intel.com/design/pentium4/ KR

  22. Useful Web Sites (3) • Intel Desktop Boards (Motherboards): http://developer.intel.com/design/motherbd/ • PC Design Guide (Microsoft and Intel): http://www.pcdesguide.org/ • AMD Home: www.amd.com • AMD Athlon: http://www.amd.com/products/cpg/athlon/index.html • PC Guide: http://www.pcguide.com/index.htm KR

  23. Useful Web Sites (4) • Barry B Brey's personal web-site with some PC and microprocessor hints • http://users1.ee.net/brey/ • Exercise look up Brey’s description of a Microprocessor at • http://members.ee.net/brey/l16.htm KR

  24. Year Processor Clock Bus Width Addressable Memory Virtual Mem Transistors Comments 1978 8086 5MHz -> 10MHz 16-bits 1MB - 29000 First 8086 – used in IBM/PC clones 1979 8088 5MHz -> 8MHz 8-bits 1Mb - 29000 Used in IBM/PC & PC/XT 1982 80286 6MHz -> 12.5MHz 16-bits 16Mb 1Gb 134000 Used in PC/AT 1985 80386DX 16MHz -> 33MHz 32-bits 4Gb 64Tb 275,000 32-bit CPU & ext bus Evolution of Intel 80x86 Family KR

  25. Year Processor Clock Bus Width Addressable Memory Virtual Mem Transistors Comments 1989 80486DX 25MHz -> 50MHz 32-bits 4Gb 64Tb 1.2 million L1 Cache on chip, also on-chip FPU. 486 derivatives still around in low-cost internet appliances 1993 Pentium 60MHz – 100MHz 64-bits 4Gb 64Tb 3.1 million Superscalar architecture 1995 Pentium Pro 150MHz -> 200MHz 64-bits 4Gb 64Tb 5.5 million Dynamic execution architecture drives high-performing processor, integrated L2 Cache 1997 Pentium II 200MHz -> 533MHz 64-bits 4Gb 64Tb 7.5 million Dual independent bus, dynamic execution, Intel MMXTM technology KR

  26. Exercise • Visit the Intel Processor Hall of Fame http://www.intel.com/intel/museum/25anniv/hof/hof_main.htm • Visit the Pentium III and P4 Home pages and also the AMD K6-3D Now and Athlon pages • Identify the unique new feature(s) of each processor • Write out entries for Pentium III, P4, IA-64 and Athlon that could be included in the Hall of Fame at a future date. KR

  27. Review Of MPU Fundamentals • For Simplicity look at a simple model of an MPU • 8-bit • 64K address space • Intel style interface KR

  28. Simplified Block Diagram of a Microcomputer KR

  29. Diagram of a Generic Microprocessor KR

  30. General Registers • Small set of internal registers - temporary data storage • CU ensures that data from the correct register is presented to the ALU • CU ensures that data is written back to correct register • Accumulator usually holds ALU result KR

  31. Status or Flags Register (Example) KR

  32. Program Counter Register • Points to the next register to be executed • Called Instruction Pointer in Intel x86 Architecture KR

  33. Stack Pointer • STACK: Part of memory where program data can be stored by a simple PUSH operation • Restore data by a POP • Stack is in main memory and is defined by the program • Stack Pointer (SP) keeps track of the next location available on the Stack • Organised as a FILO Buffer KR

  34. Stack Exercise • At the start of the following sequence the Stack Pointer has the value C000h. The following code is executed • PUSH AL ; Push 8 bit accumulator data • PUSH PSW ; Push 8 bit flags register • What is the value of the SP at this point? • The following instructions are executed without any further stack activity in the meantimePOP PSW ; Restore 8 bit flags register • POP AL ; Restore 8 bit accumulator data • What is the value of the SP at this point? Note how the POP order is the reverse of the PUSH order. KR

  35. Simple Microprocessor Model KR

  36. Fetch-Decode-Execute KR

  37. Fetch-Decode-Execute (Memory) KR

  38. Instruction Cycle Examples KR

  39. Memory Map KR

  40. Simple Memory Devices (8K PROM & RAM) KR

  41. Memory Read and Write Cycles • Hardware Control lines used by the CPU to Control reads and Writes to Memory • Active low signal RD# asserted for a Read Cycle • Active Low signal WR# indicates a write • RD# and WR# signals supply timing information to memory device KR

  42. Read Cycle KR

  43. Read Cycle Timing Diagram KR

  44. Write Cycle KR

  45. Write Cycle Timing Diagram KR

  46. Input and Output Cycles • Intel Architecture processors have an I/O address space, separate from memory (Code and Data) • Allow I/O devices to be decoded separately from memory devices • Use IOR# and IOW# signals for Input & Output • Exercise: Draw Input & Output Cycles following the memory cycle examples KR

  47. I/O Instructions • Separate I/O instructions cause the IOR# or IOW# signals to be asserted • MOV AL, (400Fh) ; instruction provides 16-bit address • IN AL, 2Ch ; instruction provides an 8-bit address • Some processors only support a single address space - I/O devices are decoded in the memory map KR

  48. Advantages of Memory Mapped I/O • I/O locations are read/written by normal instructions - no need for separate I/O instructions • Size of instruction set reduced • Memory manipulations can be performed directly on I/O locations • No need for IOR# and IOW# pins KR

  49. Advantages of Separate I/O Mapping • All locations in memory map are available for memory • No block removed for I/O • Smaller, faster instructions can be used for I/O • Less Hardware decoding for I/O • Easier to distinguish I/O accesses in assembly language • Which mapping system is preferable? Why? KR

  50. Processor with multiple memory devices How do you allow many memory devices to drive the same bus? KR

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