1 / 66

COPING WITH INTERCONNECT

COPING WITH INTERCONNECT. Impact of Interconnect Parasitics. Nature of Interconnect. INTERCONNECT. Capacitance: The Parallel Plate Model. Typical Wiring Capacitance Values. Fringing Capacitance. Fringing Capacitance: Values. How to counter Clock Skew?. Interwire Capacitance.

melyssa-simpson
Télécharger la présentation

COPING WITH INTERCONNECT

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. COPING WITH INTERCONNECT

  2. Impact of Interconnect Parasitics

  3. Nature of Interconnect

  4. INTERCONNECT

  5. Capacitance: The Parallel Plate Model

  6. Typical Wiring Capacitance Values

  7. Fringing Capacitance

  8. Fringing Capacitance: Values

  9. How to counter Clock Skew?

  10. Interwire Capacitance

  11. Interwire Capacitance

  12. Impact of Interwire Capacitance

  13. Capacitance Crosstalk

  14. How to Battle Capacitive Crosstalk

  15. Driving Large Capacitances

  16. Using Cascaded Buffers

  17. tp in function of u and x

  18. Impact of Cascading Buffers

  19. Output Driver Design

  20. How to Design Large Transistors

  21. Bonding Pad Design Bonding Pad GND 100 mm Out VDD Out In GND

  22. Reducing the swing • Reducing the swing potentially yields linear reduction in delay • Also results in reduction in power dissipation • Requires use of “sense amplifier” to restore signal level

  23. Charge Redistribution Amplifier

  24. Precharged Bus

  25. Tristate Buffers

  26. Using Bipolar Versus MOS But: Bipolar does not scale well with voltage!

  27. Bipolar Versus MOS (cont.)

  28. INTERCONNECT

  29. Wire Resistance

  30. Interconnect Resistance

  31. Dealing with Resistance

  32. Polycide Gate Mosfet

  33. Modern Interconnect

  34. RI Introduced Noise

  35. Power and Ground Distribution

  36. Electromigration (1)

  37. Electromigration (2)

  38. RC-Delay

  39. RC-Models

  40. Reducing RC-delay Repeater

  41. The Ellmore Delay

  42. Penfield-Rubinstein-Horowitz

  43. INTERCONNECT

  44. Inductive Effects in Integrated Circuits

  45. L di/dt

  46. L di/dt: Simulation

  47. Choosing the Right Pin

  48. Decoupling Capacitors

  49. The Transmission Line

  50. Lossless Transmission Line - Parameters

More Related