GBT K-band Focal Plane Array

1. GBT K-band Focal Plane Array Monitor and Control Interface, Cryogenic LNA Bias System February 27, 2008

2. Existing Bias TechnologyKFPA Requirements • Cryo LNA Bias Cards • 4 or 6 bias channels/card, screwdriver adjusted Vdrain and Vgate, servo Idrain. • Card caged, each card 8.5 x 4.5 x 0.5”, 28 in 3 sp. – 19” Rack. • 2 wires per amp stage plus ground via hermetic feedthrough. • KFPA will have 61 pixels, 2 polarizations, 4 amp stages: • 488 Vdrain, 488 Vgate, 122 LED lines, plus grounds. • 82 – 6 channel cards, 12 rack spaces (21”) • 1220 pin hermetic feed through including LEDs and grounds • Decision: • Bias regulators inside the dewar, adjust them remotely. • LNA Bias becomes more dependant on M+C

3. Existing NRAO M+C Technology • VLBA Standard Interface Board • 256 Control bits, 256 Monitor bits, 64 Analog channels • 8032 @ 11 MHz • RS-485 @ 57k • GBT Gregorian Receiver Interface • 48 Control bits, 50 Monitor bits, 56 Analog channels, 8 Analog sources • 8052 @ 11 MHz • RS-485 @ 57k • RF attenuating enclosure, filtered connectors, 12 x 7 x 4” • Analog channels are 12 bits

4. KFPA Monitor and Control Needs • ~2000 Analog monitor points • 488 Cryo LNA stages, Vd, Id, Vg • 61 Noise cal Id, plus overall Vd, Vg • 61 I-LED • 61 Down Converter LO levels, Amplifiers bias • 15K, 50K, 300K, Vacuum, Power Supplies • >7000 Digital M+C points • 61 Down Converter Attenuators x2, 4-5 bits • 488 Cryo LNA stage bias settings, 8 bits • 61 LED On/Off • Cryo state, S/R, Cal State… • Thousands of wires, 1-2m long.

5. KFPA Monitor and Control Needs • Increase Monitor and Control distribution • Build M+C capability into individual receiver modules. • Use serial lines for communication with modules. • Ethernet to GBT Network with COTS single board as go-between. • Benefits • Fewer dewar feed throughs. • No long line problems. • COTS: Inter-Integrated Circuit (IIc, I2C, I2C). • Disadvantages • New for GB Receiver • Interference, Clock runs at 400 kHz

6. Cryogenic LNA Bias, ALMA 40.04.02.01

7. Cryogenic LNA Bias

8. Cryogenic LNA Bias • ALMA 40.04.02.01 Bias regulator circuit. • 8 - Dual, non-volatile, 8 bit, IIc potentiometers controlling voltage references to create Vdrain-set and Idrain-set for regulator. • Two 10 bit, 12 channel, IIc A/D converters, scaled, monitor Vd, Id, Vg, I-LED (drop two Vg measurements on later amp stages). • Each pixel enabled or isolated by IIc bus buffer, selected by IIc I/O Expander external to the pixel. • Bias and Monitor for both polarizations fits on 2 x 3” PC card, 61 cards and mother board fit in 9 x 9 x 4”. • Bias card array is contained in a pod off the dewar.

9. Monitor and Control

10. Monitor and Control • Each module contains IIc A/D’s and I/O Expanders and is enabled or isolated by IIc bus buffer, selected by IIc I/O Expander external to the module. • Additional IIc M+C boards constructed for non-module monitor and control functions. • Multiple IIc busses isolate subsystems and decrease M+C scan time.

11. Summary and Comments • Thousands of Monitor and Control points distributed over entire receiver chassis communicating via a serial bus instead of points wired to a central unit. • COTS single board computer interfaces between M+C nodes and GBT M+C System and is located outside the dewar. • RFI Mitigation: • We strongly advise not running M+C scans during observing scans, rather in between scans. • A/D converters will be set for external (bus) clock, single board computer is enclosed in an RF attenuating enclosure, low pass feed throughs will be used.