K-Maps, Timing Sequential Circuits: Latches & Flip-Flops

K-Maps, TimingSequential Circuits: Latches & Flip-Flops Lecture 4 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier, 2007

2.7 3-input K-map

3-input K-map

K-map Definitions • Complement: variable with a bar over it • Literal: variable or its complement • Implicant: product of literals • Prime implicant: implicant corresponding to the larges circle in the K-map

K-map Rules • Each circle must span a power of 2 (i.e. 1, 2, 4) squares in each direction • Each circle must be as large as possible • A circle may wrap around the edges of the K-map • A one in a K-map may be circled multiple times • A “don't care” (X) is circled only if it helps minimize the equation

4-input K-map

Don’t Cares

Contention: X • Not just 1’s and 0’s • Contention: X

Floating: Z Tri-state Buffer

2.8 Building Blocks • Multiplexer vs. Demultiplexer • Decoder vs. Encoder • Priority Encoder • Adder

Multiplexers

Decoders

2.9 Timing • See chap08.ppt of last year.

2.9.1 Propagation & Contamination Delay • Propagation Delay: tpd = max delay from input to output • Contamination Delay: tcd = min delay from input to output

Critical (Long) and Short Path

2.9.2 Glitches • Glitch: when a single input change causes multiple output changes • Glitches don’t cause problems because of synchronous design conventions (which we’ll talk about in a bit) • But it’s important to recognize a glitch when you see one in timing diagrams

Glitches: Example

Ch.3 Sequential Circuits • Circuits that: • give sequence to events • have memory (short-term) • use feedback from output to input

3.2 State Elements • State: information that determines future behavior of circuit • State elements store state • Cross coupled inverter pair • SR Latch • D Latch • D Flip-flop

Cross Coupled inverter pair

3.2.1 SR Latch • Bistable circuit

3.2.2 D Latch

3.2.3 D Flip-Flop How many transistors required for a D-FF ?

3.2.4 Registers

3.2.5xEnabled & Resettable FF

Eg.3.2– D-FF vs. D Latch

D Flip-Flop Input Timing Constraints • Setup time: tsetup = time before the clock edge that data must be stable (i.e. not changing) • Setup time: thold = time after the clock edge that data must be stable • Aperture time: To = time around clock edge that data must be stable

D Flip-Flop Output Timing • Propagation Delay: tpcq = time after clock edge that Q is guaranteed to be stable (i.e. stop changing) • Contamination Delay: tccq = time after clock edge that Q might be unstable (i.e. start changing)

3.3 Synchronous Logic Design • 3.3.1 Some Problematic Circuits

3.3.2 Sync. Seq. circuits

3.4 Finite State Machines • Moore & Mealy Machine

3.4 Finite State Machines

3.4.2 State Encoding • Divide by N counter

Next Time • Finite State Machines

K-Maps, Timing Sequential Circuits: Latches & Flip-Flops