Final Project Presentation

1. Final Project Presentation Design and ASIC Implementation of Low-Power Viterbi Decoder for WLAN Applications Academic Guide 1: Academic Guide 2:

2. Aim and Objectives of the Project • AIM : • To design and implement a low power Viterbi decoder for WLAN applications in ASIC using 130nm CMOS technology • Objectives • To review the literature on low power Viterbi decoder, WLAN and low power ASIC design algorithms and architecture. • To arrive at design specifications of Viterbi decoder based on applications and to identify the suitable architecture. • To develop a software reference model of the Viterbi decoder based on the derived specification • To develop a hardware module of the Viterbi decoder based on the derived specification. • To implement the Viterbi decoder using ASIC flow. • To verify the completed design to meet the specifications.

3. Introduction • Problem of digital communication – Transmit much data via a noisy channel – Detect and correct errors • WLANs are flexible data communication systems implemented as the extensions or alternative to the wired LAN. • The 802.11a uses OFDM technique . 802.11a Receiver Block Diagram[1]

4. Introduction • A convolutional coding is a class of error correcting codes which are widely used as channel coder in today’s digital communication systems. • Viterbi Decoder is commonly used in decoding convolutional codes for wireless communication. • VDs are widely used as forward error correction (FEC) blocks in many digital communication applicationssuch as mobilephones, video and audio broadcasting receiver,modems and WLANs. • Viterbi algorithm was devised by Andrew J. Viterbi in 1967. Convolutional Encoder[9] N-state Trellis

5. Literature Review (Summary) • Basic Architecture of the VD has 3 major building blocks: BMU (branch metric Unit), ACSU (add-compare-select Unit), (SMU) Survivor Memory Unit • 64 add-compare-select (ACS) operations • There are no comparisons and selections to be made for the first 6 stages. • Trace back length => 4 or 5 x K [4] • The free distance Dfree = 10 for K=7 • ACS unit consumes most power and area [1]. • There are two ways of implementing the SMU: Register exchange and trace back method. • Traceback method consumes less area and power but has high design complexity Basic Architecture of Viterbi decoder [1]

6. Literature Review Specifications of the Viterbi decoder are as given below:

7. Matlab Simulation Results Original Data Decoded Data Matlab Simulation results obtained are as shown below: ` Input Data: 0001110011100010010000100001111010010101100000000 Encoded data with noise

8. Design Procedure C T R L BMU Distance ACS LowestState TBU Block Diagram of Architecture of Viterbi Decoder Decoded output Code PathMetric Address Survivors Reset Address Data Control & Clock Signals Bus Active C L O C K RAM Metric RAM Survivor MMU Clock Address Data

9. Design Procedure continued . . • The BMU calculates the distance between the received symbols and code words on the branches. • The ACS units perform comparison among candidate paths to determine survivors and compute the corresponding path metrics. Conventional ACSU architecture Low power ACSU(CSA) architecture

10. Design Procedure continued . . • The memory management unit (MMU) governs the operations of SMU • The clock and control unit are used to generate the clock and control signal respectively • The trace back algorithm implemented could be described as follows : • 1. At time t when TB_EN=1 get the lowest state from ACS. • 2. From the survivor memory, get survivor value of those node. • 3. Concatenate the lowest state and survivor bit and shift. • 4. Traceback the shortest path to obtain the decoded output MMU Control Signals

11. Design Procedure continued . . Design of Hardware Model • Hardware modeling of Viterbi Decoder is done in Verilog HDL using ModelSim. • Design of sub-blocks – ACS unit, Branch metric unit and Survivor Memory unit. • Design of Controller unit and Clock unit to provide control signals and clock signals for all the above sub-blocks. • Integration of all the above sub-blocks to complete the Viterbi decoder block. • Apart from the decoder design, a convolutional encoder was also designed for testing the viterbi decoder for different test cases

12. Hardware Design Flow Chart HDL coding GDSII Generation Synthesis, Optimization Physical verification Formality Place and Route Scan insertion Floor planning and Power planning Static Time Analysis No Timing met Yes

13. Design Procedure continued . . Control Unit Clock Gen Unit BMU ACSU TBU MMU • Schematic of Viterbi Decoder obtained in DC Decoded output RAM Active Reset Clock Code

14. Design Procedure continued . . Testbench • Test Bench Setup Viterbi Decoder Code Word Input Data Convolutional Encoder Decoded Output Input Data :0001110011100010010000100001111010010101100000000 Code word : 1110110001111010010101110110110001010000011000011100010010010000 0010110000100111110010101001101011011001011000111001000110110000

15. Simulation Results continued . . Input Data: 00011 10011 10001 00101 00100 00111 10100 10101 10000 0000 Encoder O/P & Decoder output Input Data : 00011 10011 10001 00101 00100 00111 10100 10101 10000 0000 Encoder out : 1110110001111010010101110110110001010000011000011100010010010000 0010110000100111110010101001101011011001011000111001000110110000 Decoded Output : 00011 10011 10001 00101 00100 00111 10100 10101 10000 0000 VD O/P with no error at input

16. Simulation Results continued . . Input Data : 00011 10011 10001 00101 00100 00111 10100 10101 10000 0000 Code word: 1110110001111010010101110110111000000010011000011100010010010000 0010110000100111110010101001101011011001011000111001000110110000 Decoded Output : 00011 10011 10001 00101 00100 00111 10100 10101 10000 0000 VD O/P with 4-bit error (near-by error) at input Code word: 1110110001111010010101110110110000000000011000011101010010010000 0010110000100110110010101001101011011001011010111001000110110000 VD O/P with 4-bit error (Far-away error) at input

17. Simulation Results continued . . Input Data :00011 10011 10001 00100 00100 00111 10100 10101 10000 0000 Code word : 1110110001111010010101110110110001010000011000011100010010010000 0010110000100110110010001000100011010001011000011101000110110000 Decoded Output :00011 10011 10001 00100 00110 01111 01001 01011 00000 0000 VD O/P with 6-bit error at input

18. Design Synthesis The synthesis results are as shown below:

19. Physical Design Results Placement CTS Total number of cell instances: 9999 Total number of nets: 12103 Total number of ports: 9 Core Width = 503.7 mm2 Core Height = 503.3 mm2

20. Physical Design Results Routing IRDrop Power Report Total switching power = 5.677 mW Total internal power = 3.40231 mW Total short-circuit power = 20.2082 mW Total leakage power = 0.4688 mW Total power = 29.7567 mW IR Drop Max voltage drop (mV) = 2.896 (VDD)

21. My contribution • A convolutional encoder was designed based on the 802.11a specification • Reduced the total no ACS units from 64 to 4 ACS, thereby power reduction was achieved. • An ACS unit was designed with a parallel architecture. • Clock gating was used for reducing the power.

22. Conclusion • Usage of CSA architecture lowers down hardware complexity as well as power dissipation to 29.75 mW which is a reduction of 44% when compared to the reference design • Reducing the number of ACS units to 4 from that used in other Viterbi Decoders reduces the area by 94% • The width of the RAM influences the Data rate, the current width of 8 results in data rate of 1.56Mbps • Changing the RAM size makes the design compatible for any constraint length with very few minor modifications • The design not only considers the error correction capability, but also provides a power-efficient solution

23. Suggestions for future work • Design of soft decision Viterbi decoder • Design of a puncturing unit to achieve higher coding rates • Implementation of parallel processing blocks to increase the throughput of the system

24. Literature • Journals • C. C. Lin, Y. H. Shih, H. C. Chang and C. Y. Lee, “Design of a power reduction Viterbi decoder for WLAN application”, IEEE Trans. on Circuits and Systems-I, vol.52, no.6, pp.1148–1156, June 2005 • 2. D. A. El-dib and M. I. Elmasry, “Modified register exchange Viterbi decoder for low-power wireless communications”, IEEE Trans. Circuits Systems-I, vol.51, no.2, pp.371–378, February 2004

25. Literature (cont..) • Conference Papers 3.Maharatna, K, Troya, A, Kristic, M and Grass E, “On the implementation of a Low-Power IEEE 802.11a compliant Viterbi Decoder”, in 19th VLSI Design Conference, Hyderabad, India, pp.613-618, April 2006 • 4. C.-C. Lin, C.-C. Wu, and C.-Y. Lee, “A low power and high speed Viterbi Decoder chip for WLAN applications”, in Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC'03), Lissabon, Portugal, pp.723–726, September 2003

26. Literature (cont..) • Books • 4.Bernard Sklar,“Digital Communications - Fundamentals and Applications”, 2nd Edition, Pearson Education, ISBN:81-7808- 373-6, 2004 • 5. Simon Haykin “Communication Systems”, John Wiley & Sons, 4th Edition, ISBN: 9971-51-305-6, 2004 • 6. Samir Palnitkar, “Verilog HDL – A Guide to Design and Synthesis”, Prentice Hall, ISBN: 0-13-044911-5, 2003

27. Literature (cont..) • Websites ( accessed as on Aug. 2008) 7. http://home.netcom.com/~chip.f/viterbi/tutorial.html (A Tutorial on Convolutional Coding with Viterbi Decoding) 8. Synopsys Online Documentation

28. Literature (cont..) 9. IEEE 802.11a WLAN physical layer specifications document 10. H.L. LOU, “Implementing the Viterbi Algorithm,” IEEE Signal processing Magazine, pp.42-52, Sept. 1995

29. Thank You