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Stratix V 28G Transceiver Live Demo

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Stratix V 28G Transceiver Live Demo

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    1. Stratix V 28G Transceiver – Live Demo

    2. Outline Altera University Program Stratix V Transceiver Introduction 100G in Stratix V Stratix V SI Kit Demo Design Demo 2

    3. Altera University Program 3

    4. NetFPGA on DE4 4

    5. NetFPGA on DE4 5

    6. Stratix V FPGAs – Built for Bandwidth

    7. Stratix V Device Family Variants Stratix V GT variant 28 Gbps for high-performance, ultra-high bandwidth applications Stratix V GX variant Up to 66 transceivers at 14.1 Gbps for high performance, high bandwidth Stratix V GS variant Optimized for high-performance, high-precision DSP applications with transceivers up to 14.1 Gbps Stratix V E variant For highest density, high-performance applications

    8. Designed for Backplanes and Optical Modules Drive 40” backplanes at 14.1 Gbps 10GBASE-KR compliant (IEEE 802.3AP Clause 72) Interface to optical modules directly Built-in electronic dispersion compensation (EDC) XFP, SFP+, QSFP, and CFP compliance Signal conditioning Pre-emphasis and de-emphasis Four-stage continuous time linear equalizer (CTLE) 5-tap decision feedback equalizer (DFE) Adaptive dispersion compensation engine (ADCE) On-die instrumentation Monitor eye margin within the receiver Evaluate effectiveness of signal-conditioning techniques Generate post-equalized eye contour

    9. Flexible Transceiver Architecture Scalability and flexibility through a continuous bank of transceivers Complete PMA+PCS per channel Flexible clocking options with abundant transmit clock sources enabling up to 44 independent data rates

    10. 100G Solution in Stratix V – Line Card 10

    11. Pin Migration Stratix V GT to Stratix V GX 11

    12. Stratix V GT Si Kit 12

    13. Board Block Diagram 13

    14. Demo - Stratix V GT Design Block Diagram 14 Control/status signals routed from/to ISSnP SignalTap used for observation of other data/status signals

    15. Changing PRBS Pattern 15

    16. 4 Channel Design Each channel has its own PRBS generator and verifier All of them in serial loopback PMA signal conditioning parameters set for serial loopback Running at 25G ATX PLL 16

    17. PRBS 7–Error Count For 4 25G Channels 17

    18. PRBS 31–Error Count For 4 25G Channels 18

    19. SignalTap for ATT channel 0 – showing TX and RX 19

    21. Backup

    22. 22

    23. Serial Loopback 23

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