NS9750 - Training Hardware

1. NS9750 - Training Hardware

2. PCI-to-AHB Bridge& PCI Arbiter

3. PCI-to-AHB Bridge • Provides PCI interface to NS9750 • Act as either PCI host or device • Supports PCI 2.1 and 2.2 (specification available at www.pcisig.com) • Support 32-bit PCI mode at 33Mhz max • PCI-to-AHB Address Translation • AHB-to-PCI Address Translation • Supports 6 different memory window sizes on PCI Bus (256MB,64MB,16MB,4MB,1MB,256KB) • PCI clock to system can be provided by NS9750 • Can be configured to provide PCI Central Resource Functions, including RST# • All AHB to PCI reads done as AHB SPLIT transactions to improve bus utilization • Cross bridge error detection provided • Supports big or little endian modes on AHB bus.

4. Internal PCI Arbiter • Supports up to 3 external PCI masters using PCI arbitration rules • Rotating priority scheme • Parks bus on last granted master when bus idle • Masters that do not start a transaction within 16 PCI Clocks of the bus going idle are considered to be broken and removed from arbitration

5. PCI Hardware Configuration Pins • PCI_CENTRAL_RSC_N (Internal pull-down) • “0” -> NS9750 provides PCI Central Resource functions • RST# driven via NS9750; SERR# input to NS9750 • AD,C/BE and PAR driven low when RST# active • “1” -> NS9750 does not provide PCI Central functions • RST# configured as input; SERR# configured as output • AD,CBE, and PAR tri-stated when RST# active • RTCK (Internal pull-up) • “0” -> Disable internal arbiter • “1” -> Enable internal arbiter • BOOT_STRAP[1](Merc-ID)/BP_STAT[0](Merc) (Internal pull-up) • “0” -> CardBus Mode • “1” -> PCI Mode

6. PCI System - NS9750 as Host(Host System)

7. NS9750 Configuration Mapped to 256MB PCI space PCI Central Resource PCI arbiter enabled PCI interrupt controller PCI Device #0 System Configuration Device #1 PCI memory window mapped to 0xF000_000 Device #1 PCI IO window mapped to 0x2000_0000 Device #1 interrupt connected to INTA# Device #1 accesses to NS9750 mapped to 0x3000_0000 in NS9750 main memory NS9750 PCI window mapped to 0x1000_0000 Characteristics of Host System • Ext Device Configuration • Mapped to 128MB PCI memory space via BAR0 • Mapped to 64KB PCI IO space via BAR1 • PCI Master/PCI Device #1 • Single interrupt output

8. Enable REQ# from Device #1 to internal PCI Arbiter Enable SERR# interrupt from Device #1 Enable BAR3 to decode 256MB PCI memory window Map accesses to lower 128MB of NS9750’s PCI memory window in AHB space at 0x8000_0000 to Device #1’s PCI memory space at 0xF000_0000. Map accesses to lower 64KB of NS9750’s PCI IO window in AHB space at 0xA000_0000 to Device #1’s PCI IO space at 0x2000_0000. Map PCI accesses to NS9750 to a 256MB window in NS9750’s main memory at 0x3000_0000 Enable INTA# interrupt from Device #1 in SCM. Setup of Internal Registers Host System 1.See same example of Hardware User’s Guide for more detail.

9. Setup of Internal Registers Host System • Initialize NS9750’s BAR3 register so that it responds to a 256MB window at 0x1000_0000 in PCI memory space • Initialize Device #1’s BAR0 register so that it responds to a 128MB window at 0xF000_0000 in PCI Memory space • Initialize Device #1’s BAR1 register so that it responds to a 64KB window at 0x2000_0000 in PCI IO space See same example in Hardware User’s Guide for more detail.

10. PCI System - NS9750 as Device (Device System)

11. NS9750 Configuration Mapped to 256MB PCI space via BAR3 PCI interrupt output PCI Device #1 System Configuration Host PCI memory window mapped to 0xF000_000 Host PCI IO window mapped to 0x2000_0000 NS9750 interrupt connected to INTA# of Host Host accesses to NS9750 mapped to 0x3000_0000 in NS9750 main memory NS9750 PCI memory window mapped to 0x1000_0000 PCI RST# resets entire NS9750 when active Characteristics of Device System • Ext Host Configuration • Mapped to 128MB PCI memory space via BAR0 • Mapped to 64KB PCI IO space via BAR1 • PCI Device #0 • Provides PCI arbiter and interrupt controller • Provides PCI Central Resource Functions

12. Program static data in PCI Configuration Registers per user’s application (e.g.Max_Lat, Min_Gnt, Interrupt Pin) Enable BAR3 to decode 256MB PCI memory window Map accesses to lower 128MB of NS9750’s PCI memory window in AHB space at 0x8000_0000 to Device #1’s PCI memory space at 0xF000_0000. Map accesses to lower 64KB of NS9750’s PCI IO window in AHB space at 0xA000_0000 to Device #1’s PCI IO space at 0x2000_0000. Map PCI accesses to NS9750 to a 256MB window in NS9750’s main memory at 0x3000_0000 NS9750 must be ready for first configuration cycle on bus within 225 PCI clocks after RST# negated per PCI spec Setup of Internal Registers for Device System 1.See same example of Hardware User’s Guide for more detail.

13. Setup of Internal Registers for Device System • Initialize NS9750’s BAR3 register so that it responds to a 256MB window at 0x1000_0000 in PCI memory space • Initialize Device #1’s BAR0 register so that it responds to a 128MB window at 0xF000_0000 in PCI Memory space • Initialize Device #1’s BAR1 register so that it responds to a 64KB window at 0x2000_0000 in PCI IO space See same example in Hardware User’s Guide for more detail.

14. PCI Burst Read from NS9750 The functional timing for trdy_n,devsel_n, and the read data on ad[31:0] shows the fastest possible response from the target.

15. Hints & Kinks • If NS9750 can generate the PCI CLK, why do I have to connect the PCI_CLK_OUT pin to the PCI_CLK_IN pin? • Since the PCI Bus specification only allows for 2ns of clock skew, NS9750 must use the same clock signal as the other PCI devices. • Do I connect the IDSEL pin of NS9750 to the IDSEL pin of all of the other PCI devices? • IDSEL is an input to NS9750 and all of the other PCI devices. It is used to select a device during PCI configuration cycles. As such, IDSEL of each device must be connected to a unique member of AD[31:11] , where Device #0 is connected to AD[11]; Device #1 is connected to AD[12], etc. • Since the PCI bus uses reflected-wave switching, do I need to terminate PCI_CLK? • Yes

16. Hints & Kinks • When NS9750 is the PCI host, can IDSEL be tied low? • There is no problem with this. However, this prevents any external devices from accessing NS9750’s PCI configuration registers. • What PCI pins on NS9750 require external pull-up resistors from the system? • FRAME#,TRDY#,IRDY#,DEVSEL#,STOP#,PERR#,SERR# • INTA#,INTB#,INTC#, INTD#,REQ1#,REQ2#,REQ3#, • Any of the GNT[3:1]# signals connected to external PCI devices • What is the speed of PCI_CLK_OUT when the AHB clock is 100Mhz? • 28.4Mhz See the SCM chapter for a complete table of PCI_CLK_OUT speed for different AHB clock rates.

17. Hints & Kinks • Why does the NS9750 not retry target reads to it that take in excess if 32 PCI clocks to complete? • The PCI 2.2 specification states that a host bus bridge must issue a retry if it cannot return the data within 32 PCI clocks from the assertion of FRAME#. The PCI interface to NS9750 holds the PCI bus until the data is returned instead. In a 2 device PCI system (i.e. NS9750 and 1 external device), this is a non-issue. In a more complex system, this would prevent traffic between external devices until NS9750 returns the read data.