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CMOS Status

CMOS Status. Tony Affolder Short Introduction WG1 Status/Plans Module Geometry . UK playing a significant role: 4 of 6 chairs, 8 of 20 members. Working Group Tasks. WG1: Technical Challenges and Issues Define program to prove radiation tolerance and producability (yield)

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CMOS Status

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  1. CMOS Status Tony Affolder Short Introduction WG1 Status/Plans Module Geometry

  2. UK playing a significant role: 4 of 6 chairs, 8 of 20 members

  3. Working Group Tasks • WG1: Technical Challenges and Issues • Define program to prove radiation tolerance and producability(yield) • Sets how these can be used in a module • First gross design CMOS reticle • Define changes to ABC130 needed • WG2: Implementation Issues: • Module and mechanical systems definition • Simulation of layout • Performance enhancement from lower material and better resolution • WG3: Composition, Logistics, Funding and Scheduling of the R&D effort

  4. Summary of existing prototypes Monolithic detector – continuous readout with time measurement HVPixel– CMOS in-pixel electronics with hit detection Binary RO Pixel size 55x55μm Noise 60e MIP seed pixel signal 1800 e Time resolution <100ns Monolithic detector - frame readout Capacitive coupled hybrid detector • HVPixelMchip - frame mode readout • Pixel size 21x21μm • 4 PMOS pixel electronics • 128 on-chip ADCs • Noise: 21e (lab) - 44e (test beam) • MIP signal - cluster: 2000e/seed: 1200e • Test beam: Detection efficiency >98% • Seed Pixel SNR ~ 27 • Cluster signal/seed pixel noise ~ 47 • Spatial resolution ~ 3 m CCPD1 - capacitive coupled pixel detector Pixel size 55x55μm Noise 70e Time resolution <100ns MIP SNR 25 CCPD2 (CAPPIX) - capacitive coupled pixel detector Pixel size 50x50μm Noise 30-40e Time resolution <300ns MIP SNR 45-60 My comment: Potential has been shown to merit further investigation. No one device could show needed performance: radiation tolerance and 1 bunch crossing timing Irradiations of test pixels 60MRad – MIP SNR 22 at 10C (CCPD1) 1015neq MIP SNR 50 at 10C (CCPD2) Technology 350nm HV – substrate 20 cm uniform

  5. https://indico.cern.ch/event/298458/ CMOS reticle Architecture • Further consideration of ABCn modifications suggests that: • Digital architecture adopted as baseline • No longer strips really Hit location encoded in ~13 bits. “Strip” segment ~37mm x 800mm Most hits single, so ~11mm x 230mm resolution Most likely to be made up of 8 ~37mm x 100mm pixels OR’d together, so shape in EC can be different Individual linesto periphery 1mm pitch Periphery encode non-zero words presented to transfer buffer to ABC130 like object Simple pixel: threshold withencoding in boundary ~13 wire bonds peroutput buffer 320Mbit/s gives 8 hits/BC • At 320Mbit/s 24 hits would need ~50 wire bonds (cf 256) per ABCn and • Only half as many ABCs as for stereo options - ≈1/10th number of bonds in total

  6. In the ABCn • Analogue section removed • Same pipeline structure (synchronous) used for storage, but words • Limit is 256bits/BC ≈ 256/13 ≈ 19 hits - Is this enough for jet core? 2x2cm • [would be 38 if two ABC used for reticule] • DCL section revised • Digital RX replaces analogue section • Power Consumption • 1W/cm^2 is upper limit (driven by time walk requirement) • Clever design should reduce this by a factor of two or three

  7. Reticle Geometry • One question is efficiency of CMOS • Can start with inactive areas which are not in overlaps • Space between reticles • Inactive edges of reticles next to edge • I have no idea what these can be • Estimates given where roughly ~80-120 mm at edge of reticles and ~80-120 mm between reticles • NEED TO FIRM UP THIS ESTIMATE • From our presentation at the CMOS TF meeting, Tim Jones came up with the following sketch of reticle Active Area 512 pixels wide (~37.5 um each) x 32 pixels long (~800 um each) From Tim Jones

  8. Module Design • Layout of module critically depends on CMOS yields • If too low, will have to build out of single reticles • If high enough, can cut multi-reticle blocks • CMOS made on 8” wafers • Really inefficient for 10 cm width • Prefers 8 cm width greatly • Would have same preference if go to 8” planar wafers • So if yield high, would end up with modules 1x4 reticles wide ( ~24 x76 mm) • Otherwise, module can be made up of 24x 19 mm sections, but would need a carry material to make a module 1x5 reticle sections 1x4 reticle sections

  9. Module Architectures • Not pursuing 2d stitching • Not possible at most foundries • Could have huge cost implications (cost per wafer and yield) • With 2d info in CMOS sensor, benefit of stitchingminimized • We assuming base module element will be a 4-5 reticle wide x 1 reticle long object • Might make sense to build modules out of two of these with peripheries pointing out • Alternate modules on opposite sides of support material with overlapping active areas Stave with alternating 48 mm modules

  10. “Low” Yield Option (I) • If yield is low (<90-95%), cost benefits will hard to achieve unless modules assembled out of single good reticles • Width of module independent of CMOS wafer size • Lowest mass method to do this is to use hybrid to tie reticles together • Required spacing between die and its precision isn’t obvious • In discussions with Tim, it may be more difficult to cool middle dies • No lateral cooling between dies (in silicon) • Cooling would have to be through face sheets to pipes

  11. “Low” Yield Option (II) • A higher mass method would be to have a carrier with good thermal properties (CF, ceramics, TPG,..) which reticles are attached • Or you could extend hybrid flex to provide in-between option

  12. “Higher” Yield Option • If yield is higher (>90-95%), could dice reticles out into bigger sections. • Width of module would be set by best use of 8” CMOS wafer size • Have benefits for handling and thermal management • Hybrids could be done as now • If this option chosen, we will ask foundries if dead areas between reticles diced together can be minimized • For AMS and Lfoundry , it is ~80 microns dicing street with similar length between the last active element and the dicing street

  13. Radiation Length • Current radiation length of a stave • Cores (including tapes): 0.72% • 2 Planar Modules: 1.08% • Total: 1.8% • For CMOS assume no additional material in carrier • Drop-in Stereo and Z-Encoded (100 micron thick sensors): • 1 Drop-in Module: 0.31% • Total: 1.03% It is possible that core can be reduced with CMOS sensors Most of material improvement made with going to single modules with 2d information

  14. Open Questions to Answer • Requirements before proceeding • Is CMOS radiation tolerant? • Can large areas be made? What is the yield, etc.?? • Is both coordinates from one layer OK – otherwise CMOS is not cheaper • Are non-pointing end-region strips OK – otherwise CMOS is not cheaper • Details for implementation: • How much of a benefit is the reduced material (how thin to go?) • How will the material behave mechanically? • Will it need cooling, i.e. min operating temperature? What is its power? • Maximum number of hits in a 2 x 2cm region – pileup and physics • There is ‘no’ charge sharing, simple track hit rates is enough • 1% current design occupancy -> 3 hits only but for jet cores? 3+ year program of R&D needed to show CMOS is a viable technology has been outlined. Many potential breakpoints were program will not work for ATLAS.

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