Topics

1. Topics • SRAM-based FPGA fabrics: • Xilinx. • Altera.

2. SRAM-based FPGAs • Program logic functions, interconnect using SRAM. • Advantages: • Re-programmable; • dynamically reconfigurable; • uses standard processes. • Disadvantages: • SRAM burns power. • Possible to steal, disrupt configuration bits.

3. Logic elements • Logic element includes combinational function + register(s). • Use SRAM as lookup table for combinational function.

4. LUT-based logic element n inputs 1 Lookup table configuration bits out Can multiplex at output or address at input

5. 111 111 1, 1, 1, 1, 1, 1, 1, 0 0, 1, 1, 0, 1, 0, 0, 1 Example 0 1

6. Evaluation of SRAM-based LUT • N-input LUT can handle function of 2n inputs. • All logic functions take the same amount of space. • All functions have the same delay. • SRAM is larger than static gate equivalent of function. • Burns power at idle. • Want to selectively add register to LE:

7. D Q Registers in logic elements • Register may be selected into the circuit: Configuration bit LUT LE out

8. Other LE features • Multiple logic functions in an LE. • Addition logic: • carry chain. • Partitioned lookup tables.

9. Xilinx Spartan-II CLB • Each CLB has two identical slices. • Slice has two logic cells: • LUT. • Carry logic. • Registers.

11. Spartan-II CLB details • Each lookup table can be used as a 16-bit synchronous RAM or 16-bit shift register. • Arithmetic logic includes an XOR gate. • Each slice includes a mux to ocmbine the results of the two functino generators in the slice. • Register can be configured as DFF or latch. • Has three-state drivers (BUFTs) for on-chip busses.

12. Spartan-II CLB operation • Arithmetic: • Carry block includes XOR gate. • Use LUT for carry, XOR for sum. • Each slice uses F5 mux to combine results of multiplexers. • F6 mux combines outputs of F5 muxes. • Registers can be FF/latch; clock and clock enable. • Includes three-state output for on-chip bus.

13. Altera APEX II logic element • Each logic array block has 10 logic elements. • Logic elements share some logic.

15. Apex II LE modes • Modes of operation: • Normal. • Arithmetic. • Counter.

16. APEX-II LE normal mode

17. APEX-II LE arithmetic mode

18. APEX-II LE counter mode

19. APEX-II LE control logic

20. D Q Programmable interconnect • MOS switch controlled by configuration bit:

21. Programmable vs. fixed interconnect • Switch adds delay. • Transistor off-state is worse in advanced technologies. • FPGA interconnect has extra length = added capacitance.

22. Interconnect strategies • Some wires will not be utilized. • Congestion will not be same throughout chip. • Types of wires: • Short wires: local LE connections. • Global wires: long-distance, buffered communication. • Special wires: clocks, etc.

23. Paths in interconnect • Connection may be long, complex: LE LE LE LE LE Wiring channel LE LE LE LE LE Wiring channel LE LE LE LE LE

24. Interconnect architecture • Connections from wiring channels to LEs. • Connections between wires in the wiring channels. Wiring channel LE LE

25. Interconnect richness • Within a channel: • How many wires. • Length of segments. • Connections from LE to channel. • Between channels: • Number of connections between channels. • Channel structure.

26. Segmented wiring Length 1 Length 2

27. Offset segments

28. Switchbox channel channel channel channel

29. Spartan-II interconnect • Types of interconnect: • local; • general-purpose; • dedicated; • I/O pin.

30. Spartan-II general-purpose network • Provides majority of routing resources: • General routing matrix (GRM) connects horizontal/vertical channels and CLBs. • Interconnect between adjacent GRMs. • Hex lines connect GRM to GRMs six blocks away. • 12 longlines span the chip.

31. Spartan-II routing • Relationship between GRM, hex lines, and local interconnect:

32. Spartan-II three-state bus • Horizontal on-chip busses:

33. Spartan-II clock distribution

34. APEX II interconnect row column

35. Spartan-II I/O • Supports multiple I/O standards: • LVTTL, PCI, LVCMOS2, AGP2X, etc. • Provides registers. • Programmable delay for pin-dependent hold time. • Programmable weak keeper circuit.

36. Spartan-II I/O block diagram

37. Configuration • Need to set all configuration SRAM bits: • minimum pin cost; • reasonable speed. • Configuration can also be read back for testing.

38. Configuration ROM • Configured on start-up from ROM: FPGA Configuration memory

39. Spartan-II configuration • Configuration length depends on size of chip: • 200,000 to 1.3 million bits. • Configuration modes: • Master serial for first chip in chain. • Slave serial for follow-on chips. • Slave parallel. • Boundary-scan.

40. Scan chain • Scan chain: shift register used to access internal state. • Logic-sensitive scan design (LSSD): scan structure that uses some hardware for normal mode and scan.

41. JTAG boundary scan • JTAG: Joint Test Action Group. • Boundary scan: • provide scan chain at pins; • allow control of chip interior; • decouple chip from rest of board for test.

42. Chip-on-board testing • Boundary scan decouples chips: board

43. Boundary scan concepts • TAP: test access port. • Requires three pins not shared with other logic. • Test reset, test clock, test mode select, test data in, test data out. • TAP controller recognizes pins, controls boundary scan registers. • Instruction register defines boundary scan mode.