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목 차

목 차. 1. HDL 소개 및 설계방법 2 . 간단한 VHDL Modeling 2 . 디지털 변복조 방식 3. DQPSK CODING TECHNIQUES 부록 : ALTERA 설치 및 사용법. HDL 소개 및 설계방법. Why need such HDLs ?. HDL 소개 및 설계방법. The lack of a formalized description makes the task of simulation and verification difficult

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목 차

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  1. 목 차 • 1.HDL 소개 및 설계방법 • 2. 간단한 VHDL Modeling • 2. 디지털 변복조 방식 • 3. DQPSK CODING TECHNIQUES • 부록: ALTERA 설치 및 사용법 SungKyunKwan Univ.

  2. HDL 소개 및 설계방법 • Why need such HDLs ? SungKyunKwan Univ.

  3. HDL 소개 및 설계방법 • The lack of a formalized description makes the task of simulation and verification difficult • The lack of documentation during the design process make maintaining and re-targeting the design difficult. • Formalized input can be used for documentation, simulation, verification and synthesis. • The design description also serves as a good exchange medium between different user, as well as between user and design tools. SungKyunKwan Univ.

  4. HDL 소개 및 설계방법 • Programming Language Features for HDLs • Data Types • format (e.g., number of bit) • types (e.g., Boolean, integer, floating point) • data representation (e.g., signed/unsigned) • Operators and Assignment Statements • arithmetic , Boolean , logic , bit manipulation , array access SungKyunKwan Univ.

  5. HDL 소개 및 설계방법 • Control Constructs • if-then-else , case , loop • Execution Ordering • sequential , concurrent • Hardware-Specific HDL Features • Interface Declarations • Port(size, mode) • size (e.g., num-bit), hardware-specific feature (e.g., Whether the port is buffered or tristate), mode (e.g., input, output, input-output) SungKyunKwan Univ.

  6. HDL 소개 및 설계방법 • Structural Declarations • The specification of registers, counter, other H/W structures that are to be used like variables in the HDL description. • RT and Logic Operators • Bit -level logical operator • bit shifting, bit rotation, bit-stream extraction …. • RT-level operator • increment and decrement operator for variables. SungKyunKwan Univ.

  7. HDL 소개 및 설계방법 • Asynchrony • In addition to synchronous behavior, RT-level hardware typically exhibits asynchronous behavior in the form of set, reset and interrupts. • Hierarchy • As designs get more complex, we naturally resort to hierarchy as a means of describing, managing and capturing the complex behavior • Procedural, structural, behavioral and design hierarchy SungKyunKwan Univ.

  8. HDL 소개 및 설계방법 • Interprocess CommunicationFor purely synchronous designs, this communication can be embedded within the process’behavioral description, since each process operates in a lock-step manner. In such case, the user can explicitly describe the communication using standard HDL constructs to force reads and writes on correct clock cycle. • Parameter passing • Message passing SungKyunKwan Univ.

  9. HDL 소개 및 설계방법 • Constraints • Constraints on the design behavior guide the synthesis of the design towards feasible realization in term of performance, cost, testability, reliability, and other physical restrictions. • User allocation and Bindings • HDL FormatTo support design description and modeling, we need a variety of HDL formats that suit different application and users. SungKyunKwan Univ.

  10. HDL 소개 및 설계방법 • Textual HDLs • ISPS, Sliage, VHDL, HardwareC, MIMOLA… • Graphical HDLs • Tabular HDLs • Tabular descriptions provide a concise notation for state-based design description, particularly for FSDMs • Waveform-Based HDLs SungKyunKwan Univ.

  11. HDL 소개 및 설계방법 • Timing diagrams can graphically represent change on signals, can show sequencing of events, and can also effectively show timing relationships between event. • Matching Language to Target Architecture Entity Full_Adder is port(X,Y : in bit; CIN : in bit; SUM : out bit; COUT: out bit); end Full_Adder; SungKyunKwan Univ.

  12. HDL 소개 및 설계방법 Architecture behave of Full_Adder is signal S1,S2,S3:bit begin S1 <= X xor Y; SUM <= S1 xor CIN after 3 ns; S2 <= X and Y; S3 <= S1 and CIN; COUT <= S2 or S3 after 5 ns; end; SungKyunKwan Univ.

  13. HDL 소개 및 설계방법 • Modeling Guidelines for HDLsIn order to achieve effcient hardware synthesis, we need to match the model of the language to that of the underlying target architecture. • Combinational Designs • Hardware design is composed of an interconnection of logic gates. (Boolean VHDL operators) • Functional Designs SungKyunKwan Univ.

  14. HDL 소개 및 설계방법 • Function designs are characterized by a mixture of synchronous and asynchronous behavior, in which asynchronous event may override synchronous operation. ☞ Illustrate a functional design using an up/down counter with asynchronous set and reset • Register-Transfer Designs • RT designs correspond to the FSMD model. • RT designs have an implicit notion of states and state transitions • Behavioral Designs • Design behavior is typically expressed in a sequential language style using sequential assignment statement SungKyunKwan Univ.

  15. HDL 소개 및 설계방법 • 효율적인 모델링 기법 • 대규모 설계를 위해서는 동작적 모델링. • 구현을 위해서는 합성 가능한 구문 이용 • Process문의 sensitivity list를 검사. • 연산 순서를 조정한 모델링 SungKyunKwan Univ.

  16. HDL 소개 및 설계방법 • 연산수행을 줄이는 모델링 • 같은 연산은 한번에 수행 process(a,b,c,d) process(a,b,c,d) begin begin y1 <= a+b; y1 <= a+b; y2 <= a+b+d;  y2 <= y1+d; y3 <= a+c; y3 <= a+c; end process; end process; SungKyunKwan Univ.

  17. HDL 소개 및 설계방법 • 보다 효율적인 문장 선택 • 빠른 속도를 필요로 하는 회로에는 case문보다 if문이 효율적이다. • Simulator에 따라 다른 library와 package사용 • Library나 각package들의 이름 및 형식은 사용 하는 simulator에 따라 다를 수 있다. • 반도체 회사에서 제공하는 library를 이용한 합성 • 관련이 많은 부분을 그룹지어 코딩 및 합성 SungKyunKwan Univ.

  18. Library ieee;use ieee.std_logic_1164.all;entity f_adder is port(x,y,c_in : in std_logic; s_out,c_out : out std_logic);end f_adder;architecture behave of f_adder isbegin process(x,y,c_in) variable tmp : std_logic_vector(1 downto 0); Full_adder 동작적 모델링 간단한 VHDL Modeling SungKyunKwan Univ.

  19. 간단한 VHDL Modeling begin l := “00”; if x=‘1’ then l := l+1; end if ; if y=‘1’ then l := l+1; end if ; if c_in=‘1’ then l := l+1; end if ; if (l=0) or (l=2) then s_out <= ‘0’ else s_out <= ‘1’;end if; if (l=0) or (l=1) then c_out <= ‘0’ else c_out <= ‘1’;end if; end process; end behave; SungKyunKwan Univ.

  20. 간단한 VHDL Modeling • Full_adder 구조적 모델링 SungKyunKwan Univ.

  21. 반가산기 모델링(Half adder)Library ieee;use ieee.std_logic_1164.all;entity h_adder is port(a,b : in std_logic; ☞ s,c : out std_logic);end h_adder;architecture behave of h_adder isbegin process(a,b) begin 간단한 VHDL Modeling if (a=b) then s <= ‘0’; else s <= ‘1’;end if; if (a=‘1’) and (b=‘1’) then c <=‘1’; else c <= ‘1’;end if; end process; end behave; SungKyunKwan Univ.

  22. OR gate 모델링Library ieee;use ieee.std_logic_1164.all;entity or2 is port(a,b : in std_logic; ☞ o : out std_logic);end or2;architecture behave of or2 isbegin process(a,b) begin 간단한 VHDL Modeling if (a=‘0’) and (b=‘0’) o <=‘0’; else o <= ‘1’;end if; end process; end behave; SungKyunKwan Univ.

  23. 전가산기 모델링(Full adder)Library ieee;use ieee.std_logic_1164.all;entity f_adder is port(x,y,c_in : in std_logic; ☞ s_out,c_out : out std_logic);end f_adder;architecture structural of or2 is signal st1,st2,st3 : std_logic; 간단한 VHDL Modeling component or2 port(a,b : in std_logic; o : out std_logic); end component; component h_adder port(a,b : in std_logic; s,c : out std_logic); end component; begin SungKyunKwan Univ.

  24. 간단한 VHDL Modeling HA1 : h_adder port map(x,y,st1,st2); HA2 : h_adder port map(st1,c_in,s_out,st3); ORG : or2 port map(st2,st3,c_out); end structural; SungKyunKwan Univ.

  25. 간단한 VHDL Modeling • Multiplexer 모델링 SungKyunKwan Univ.

  26. 간단한 VHDL Modeling • Entityentity Mux2X1 is port(a,b : in std_logic; sel : in std_logic; y : out std_logic);end Mux2X1; SungKyunKwan Univ.

  27. 간단한 VHDL Modeling • Architecture 1Architecture behave of Mux2X1 isbegin process(a,b,sel) begin if sel=‘0’ then y <= a; else y <= b; end if; end process;end behave; SungKyunKwan Univ.

  28. 간단한 VHDL Modeling • Architecture 2Architecture behave of Mux2X1 isbegin process(a,b,sel) begin case sel is when ‘0’ => y <= a; when others => y<=b; end case; end process;end behave; SungKyunKwan Univ.

  29. 간단한 VHDL Modeling • Architecture 3Architecture behave of Mux2X1 is signal temp : std_logic;begin process(a,b,sel) begin temp <= not(sel); y <= (a and temp) or (b and sel); end process;end behave; SungKyunKwan Univ.

  30. 간단한 VHDL Modeling • 동기10진 카운터 modeling • Library ieee;use ieee.std_logic_1164.all;entity cnt10 is port(ck,rst : in std_logic; q : buffer std_logic_vector(3 downto 0));end cnt10;architecture behave of cnt10 isbegin SungKyunKwan Univ.

  31. 간단한 VHDL Modeling process(ck,rst) begin if ck’event and ck=‘1’ then if rst = ‘0’ then q <= “0000”; elsif q = “1001” then q<= “0000”; else q <= q+ “0001”; end if; end if; end process; end behave; SungKyunKwan Univ.

  32. 디지털 변복조 방식 SungKyunKwan Univ.

  33. 디지털 변복조 방식 • 디지털 통과대역 변조 • ASK(Amplitude Shift Keying) • FSK(Frequency Shift Keying) • PSK(Phase Shift Keying) • QAM(Quadrature-Amplitude Modulation) SungKyunKwan Univ.

  34. 디지털 변복조 방식 SungKyunKwan Univ.

  35. 디지털 변복조 방식 • PSK(Phase Shift Keying) • 디지털 신호의 정보내용에 따라 반송파의 위상 변 화시키는 방식 • M진 PSK(M-ary Phase Shift Keying) • 2원 디지털 신호를 m개의 bit로 묶어서 개의 위상 으로 분할시킨 위상변조방식. • 2진, 4진, 8진 PSK 등이 널리 사용. • PSK파는일정한 진폭을 갖는 파형 • 전송로 등에 의한 레벨 변동의 영향을 적게 받는다 SungKyunKwan Univ.

  36. 디지털 변복조 방식 • 2진 PSK(Binary Phase Shift Keying) • 데이터( )에 따라 개개의 데이터 구간에 2종의 위 상을 갖는 정현파 중 하나를 전송하는 방식 SungKyunKwan Univ.

  37. 디지털 변복조 방식 • 4진 PSK(Quadrature Phase Shift Keying) SungKyunKwan Univ.

  38. 디지털 변복조 방식 SungKyunKwan Univ.

  39. 디지털 변복조 방식 • 차동 PSK(Differential Phase Shift Keying) • 동기검파용 기준반송파가 필요없다 • 1구간(T초)전의 PSK신호를 기준파로 사용하여 동기검파하는 방식. • 전후의 신호구간 사이의 위상차가 정보에 대응하도록 송신측에서 PSK변조하기 전에 차동부호화(Differential Encoding) 할 필요가 있다.. SungKyunKwan Univ.

  40. 디지털 변복조 방식 • 차동 PSK 송신기 SungKyunKwan Univ.

  41. DQPSK CODING TECHNIQUES SungKyunKwan Univ.

  42. DQPSK CODING TECHNIQUES SungKyunKwan Univ.

  43. DQPSK CODING TECHNIQUES • DQPSK ENCODER 구조적 모델링 SungKyunKwan Univ.

  44. 직병렬변환기 모델링Library ieee;use ieee.std_logic_1164.all;entity s_to_p is port(reset,tx_in : in std_logic; ☞bclk,sclk : in std_logic; I_ch,q_ch : out std_logic);end s_to_p;architecture behave of s_to_p is signal tmp : std_logic; begin process(reset,tx_in,bclk) DQPSK CODING TECHNIQUES begin if reset=‘0’ then tmp <= ‘0’; elsif bclk’even and bclk=‘0’ then tmp <= tx_in; end if; process(reset, TMP, tx_in, sclk) begin if reset = '0’ then i_ch <= '0'; SungKyunKwan Univ.

  45. DQPSK CODING TECHNIQUES q_ch <= '0'; elsif sclk'event and sclk = '0' then i_ch <= TMP; q_ch <= tx_in; end if; end process; end behave; SungKyunKwan Univ.

  46. DQPSK CODING TECHNIQUES • 직병렬변환기 Simulation 결과 SungKyunKwan Univ.

  47. ENCODER 모델링Library ieee;use IEEE.std_logic_1164.ALL;entity enc is port (rst, i_in, q_in : in std_logic; sclk : in std_logic; d_out : out std_logic_vector(1 downto 0));end enc;architecture behave of enc is signal C_STATE, N_STATE : std_logic_vector(1 downto 0); signal IQ_IN : std_logic_vector(1 downto 0); DQPSK CODING TECHNIQUES SungKyunKwan Univ.

  48. DQPSK CODING TECHNIQUES begin IQ_IN <= i_in & q_in; process(rst,sclk,IQ_IN) begin if rst = '0' then C_STATE <= "00"; elsif sclk'event and sclk = '0’ then case C_STATE is when "00" => case IQ_IN is when "00" => N_STATE <= "00"; when "01" => N_STATE <= "01"; when "10" => N_STATE <= "10"; when "11" => N_STATE <= "11"; when others => SungKyunKwan Univ.

  49. DQPSK CODING TECHNIQUES end case; when "01" => case IQ_IN is when "00" => N_STATE <= "01"; when "01" => N_STATE <= "11"; when "10" => N_STATE <= "00"; when "11" => N_STATE <= "10"; when others => end case; when "10” => case IQ_IN is when "00" => N_STATE <= "10"; when "01" => N_STATE <= "00"; when "10" => N_STATE <= "11"; when "11" => N_STATE <= "01"; when others => SungKyunKwan Univ.

  50. DQPSK CODING TECHNIQUES end case; when "11" => case IQ_IN is when "00" => N_STATE <= "11"; when "01" => N_STATE <= "10"; when "10" => N_STATE <= "01"; when "11" => N_STATE <= "00"; when others => end case; when others => end case; end if; end process; SungKyunKwan Univ.

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