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The Control Logic

The Control Logic. Andreas Klappenecker CPSC321 Computer Architecture. Verilog HDL. Verilog Programming. Suppose that we have a module foo Our goal is to instantiate and wire a module foon that contains n copies of the module foo .

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The Control Logic

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  1. The Control Logic Andreas Klappenecker CPSC321 Computer Architecture

  2. Verilog HDL

  3. Verilog Programming • Suppose that we have a module foo • Our goal is to instantiate and wire a module foon that contains n copies of the module foo. • Many textbooks on Verilog suggest to write down the n instance explicitly • if n = 1024 then this is not a viable option • reusability of the code would be limited

  4. foo foo foo foo foo foo foo foo Example 1 foon =

  5. Example 1 module foo(out, a,b); output out; input a, b; xor (out, a, b); endmodule module foon(out, a, b); parameter n = 8; output [n-1:0] out; input [n-1:0] a, b; foo foon[n-1:0](out,a,b); endmodule

  6. foo foo foo foo foo foo foo foo Example 2 foon =

  7. Example 2 module foo(out, a,b); output out; input a, b; xor (out, a, b); endmodule module foon(out, a, enable); parameter n = 8; output [n-1:0] out; input [n-1:0] a; input enable; foo foon[n-1:0] (out, a, {out[n-2:0],enable}); endmodule

  8. Remarks • The module vector operator is not available in Icarus Verilog nor in Veriwell • The features shown work in vcs foo foon[n-1:0](out,a,{out[n-2:0],enable}); • outandarange over [n-1:0] • {out[n-2:0], enable} gives vector [n-1:0] • The suggested for-loop construction does not work

  9. Control

  10. MIPS Multicycle Datapath Incomplete (branch and jumps…)

  11. Control • What are the control signals? • Finite state machine control • Instruction fetch • instruction decode • memory reference • R-type • branch • jump

  12. Multicycle Datapath and Control Lines

  13. High-Level Picture • What happens precisely during each step of fetch/decode/execute cycles • Construct the finite state control machine • High-level view

  14. Instruction Fetch/Decode/Execute

  15. Instruction Fetch & Decode FSM

  16. Memory-Reference FSM • Address calculation • Load sequence • read from memory • store to register • Access memory • Store sequence write

  17. R-type Instruction • Execution of instruction • Completion of instruction

  18. Branch Instruction

  19. Implementation of FSM • A FSM can be implemented by a register holding the state and a block of combinatorial logic • Task of the combinatorial logic: • Assert appropriate signals • Generate the new state to be stored in the register

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