Cost-Oriented Design of a 14-bit Current Steering DAC Macrocell

1. Cost-Oriented Design of a 14-bit Current Steering DAC Macrocell IEEE International Symposium on Circuits and Systems May 25-28th, 2003 Janusz A. Starzyk Ohio University Russell P. Mohn Sarnoff Corporation Ohio University School of Electrical Engineering and Computer Science

2. Outline • Introduction • Statistical Yield Model • Reduction of Systematic Errors • Design Cost Consideration • DAC Implementation • Conclusion and Future Work

3. Introduction • Design Consideration based On the Statistical Model • Current Source Analysis • Reference Circuit Design and Analysis • Spreading of the Composite Transistors and Random Walk • Thermometer Circuit Design • Glitches and Dynamic Performance • Architectures and Layout • Top Level Simulation Results • Estimated Design Performance

4. Organization • The DNL and INL Specifications • Design Consideration based On the Statistical Model • Segmentation of the Composite Transistors and Random Walk • Glitches and Dynamic Performance • Architectures and Layout • Simulation Results • Summary and Estimated Design Performance Figures

5. INL yield vs. relative current-source matching

6. DNL standard deviation • for the segmented architecture • B=4, so to meet the requirements for DNL

7. Segmentation of the Composite Transistors and Random Walk • depends on the transistor area A and spacing D as • where A, AVTand S are process related constants

8. Mismatch parameters as reported for various processes

9. Segmentation of the Composite Transistors and Random Walk • The random errors are determined by mismatch • The systematic errors are determined by process, temperature, and electrical gradients • In optimally designed DAC the INL and DNL errors depend only on the random errors level • Increasing transistor area reduces the random errors. • The systematic errors are layout-dependent and are minimized by transistor switching scheme.

10. Random errors - unit transistor requirements • The minimum area of the unit transistor Parameters A and AVT are technology dependent

11. The Level of Systematic Errors • where k=Acell /A>1 is a current cell layout coefficient with Acell -unit current cell area

12. Current-source Matching vs. the Design Area for 12 bit DAC Green line indicates the effect of systematic errors

13. Basic Current Source

14. Current Source Analysis uneven output voltage Iout1=13.33mA, Iout2=0 mA, Vout1=1V, Vout2=0 V

15. dI Ioff Current Source Analysis uneven output voltage In order to achieve satisfactory INL level we must keep the cut-off current low Vd src So the cut-off current is limited by Vd c Vout1 Vout2 Io

16. Current Source Analysis even output voltage Iout1=Iout2=6.66 mA, Vout1=Vout2=0.5V

17. Reference Resistor and Output Current The following empirical relation holds for Iout<20mA

18. Reference Resistor and Output Current

19. Layout specifications of the 12-bit DAC • DAC is built as a segmented architecture with 8-bit thermometer and 4-bit binary sections (to lower the glitches) • LSB cell area (1/4 of unary source cell) is A=308 m2 with W=17 m and L=18 m • 8-bit thermometer decoder is designed in two groups- one with 3 thermometer bits and second with 5 bits (MSBs) • Random walk is implemented with derived permutation sequence to minimize systematic errors • Symmetrical layout, synchronization of control signals, synchronization of unary and binary current source transistor switching, and the cascode structure of the unit current sources control dynamic performance.

20. Spreading of the Composite Transistors and Random Walk • The random errors are determined by mismatch • The systematic errors are determined by process, temperature, and electrical gradients • In optimally designed DAC the INL and DNL errors depend only on the random errors level • Increasing transistor area reduces the random errors. • The systematic errors are layout-dependent and are minimized by transistor switching scheme.

21. Reduction of Linear Systematic Errors • To compensate for linear errors a symmetrical splitting is required • Each transistor will be split into 4 locations

22. Spreading and random walk comparison

23. Permutation array

24. Wiring over the current source array

26. Wiring - via Placementin Current Sources Current sources are connected to horizontal wires sequentially

27. Wiring - Latch to Current Source Connection

28. Wiring - programmable via placement

29. Programmable via placementsecond quadrant

30. Layout • Signal S2(32) • Large capacitive load • Connects 4 symmetrically spread current sources • Unary current source 256 turned OFF

31. Layout • Signals S2(32) and S2(33) • Current sources controlled by S2(33) are far away from those controlled by S2(32) • Switching sequence designed to minimize systematic errors

32. Layout • Signals S2(32), S2(33), and S2(34)

33. Glitches • The glitch current • where Agl is the glitch amplitude, tgl is the glitch period, and t0 is the synchronization mismatch (delay time)

34. Dynamic Performance • For dynamic performance of DAC due to glitches and parasitic effects the following are recommended: • synchronize the control signals of the switching transistors; • reduce the voltage fluctuation on the drains of the current sources during switching • carefully switch the current source transistor on/off • reduce coupling of the control signals through lowering the voltage of the power supply of the latches. • increase the output resistance in high frequency applications

35. Dynamic Performance • The synchronization is achieved by equalizing each latch output load capacitance. • Using a large channel length unit current source transistor and tuning the crossing point of the switching control signals such that both switches are never switched off at the same time solves voltage fluctuation at the drain problem • Using an additional cascode transistor increases output impedance for high frequency applications • This architecture has an additional advantage of lowering glitch energy due to the drain voltage variations of the unit source.

36. Layout • 1 column (8 rows) of latches • Vertical green wires: • Latch input from D flip-flops • Latch output to current source array • Equal load

37. Simulated Test Conditions

38. Binary Driven LSB Current Sources

39. Layout • Equalizing capacitive load between binary latches and unary latches • Load determined by total length of wires to unary current sources Binary wire Unary wire

40. DNL and INL for Unbalanced Load

41. Equalizing the Binary/Unary Latch Loads

42. Digital Sine Excitations

43. Sine Output

44. Single tone output spectrum unmatched latch load

45. DNL and INL for Balanced Load Condition 2

46. DNL and INL for Balanced Load Condition 1

47. DNL and INL for Balanced Load Condition 3

48. 2^12 Ramp

49. 2^12 Ramp INL & DNL • Unbalanced capacitive unary and binary loads • INL(2^12) < 10*INL(2^7) • 17 days simulation versus 8 hours simulation

50. DNL and INL for Balanced Load Condition 1 - Vout 1.5V