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Presented by: Madhulika Pannuri Department of Electrical and Computer Engineering

Fully Redundant Clock Generation and Distribution with Dynamic Oscillator Switchover M.J. Mueller, U. Weiss, T. Webel, L.C. Alves, W.J. Clarke, M. Strasser, E. Engler, G. Cautillo, H. Osterndorf, J. Schulze. Presented by: Madhulika Pannuri

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Presented by: Madhulika Pannuri Department of Electrical and Computer Engineering

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  1. Fully Redundant Clock Generation and Distribution with Dynamic Oscillator Switchover M.J. Mueller, U. Weiss, T. Webel, L.C. Alves, W.J. Clarke, M. Strasser, E. Engler, G. Cautillo, H. Osterndorf, J. Schulze Presented by: Madhulika Pannuri Department of Electrical and Computer Engineering

  2. o The system uses two independent oscillator cards to prevent the system from going down when one oscillator fails. • o Using a multiplexer, it is possible to switch from failing oscillator to the backup oscillator. • Disadvantages: • Not capable of automatic switching. • Does not detect certain classes of failure modes. • o Introduce intelligent monitoring and switching. • o It is critical to address potential failure nodes. • o Complex firmware.

  3. Clock generation and distribution architecture

  4. The design is based on a module called ‘Intelligent Dynamic Clock Switch’ (IDCS). • o Monitors up to four oscillator signals. • o Automatically switches over to the next signal in case of a failing signal. • o The state of the input signals can be observed and reported to a control system. • All chips are given a PLL reset (ensures valid clock signals) and PLLs are locked.

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