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SciFi Tracker readout with STiC Time and Position STiC DAQ board

SciFi Tracker readout with STiC Time and Position STiC DAQ board. DAQ for STiC. 4 mezzanine cards for STiC chips are plugged to the DAQ board. Each mezzanine hosts two STiC chips

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SciFi Tracker readout with STiC Time and Position STiC DAQ board

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  1. SciFi Tracker readout with STiCTime and PositionSTiC DAQ board Presented by Guido Haefeli

  2. DAQ for STiC • 4 mezzanine cards for STiC chips are plugged to the DAQ board. Each mezzanine hosts two STiC chips • Fast control signals are daisy chained and connection implemented via RJ45 connection. Clock, Reset, Trigger and Busy are transmitted on LVDS. A 160MHz signalling clock as the system clock is used. Use 1 IN 3 OUT • SPI interface with 16 chip selects • I2C interface • Configuration of the FPGA with Altera programmer and later with Ethernet • Each STiC mezzanine receives 160MHz system clock and 640MHz TDC clock • Clock fan out is implemented on STiC mezzanine • 4 bias voltage power supplies

  3. Main features STiC • Serial data output 160Mbit/s in 8B/10B encoded, one hit is equivalent of 48bit and therefore 2.6Mhit/s can be achieved. Expected data produced by SciFi tracker is 2.5hits per track or cluster and therefore the readout allows for 1 track at 1MHz. • Synchronous running of several STiC chips by clock distribution of 640MHz • Coarse and fine delay measurement for Trigger threshold (start) and Energy threshold (stop), time over threshold can be calculated by the difference, 1.6ns time steps

  4. Single STiC requirements • Clock distribution to STiC chips, two PLLs with two reference clocks 640MHz, 2x differential LVDS pairs • System clock 160MHz, 1x LVDS differential pair • Synchronous reset 3.3V - CMOS • SPI interface 3.3V – CMOS • Power connector 2.5V and 3.3V • Power consumption of mezzanine card with two STiC chips: • 3.3V small, assume 200mA max • 2.5V 2x(0.6A + 0.9A) = 3A,

  5. STiCcard connector • 1x system clock LVDS 160MHz from clk fan-out • 1x PLL TDC clock LVDS 640MHz from clk fan-out • 2x Data link to FPGA (LVDS) • Bias SiPM and GNDA to bias connector • Connecto spare to FPGA • This is the connector on the mezzanine

  6. Light injector mezzanine IF • Small connector for the light injection mezzanine, I check the dimensions, the pinout is: • Connect D+,D- LVDS IO on FPGA • DIS 2.5 IO on FPGA • One I2C bus SCL, SCA • This is the connector on the DAQ board

  7. STiCintegrationwithcustomisedSTiC DAQ Board • Dimensions 126mm x 190mm, power supply mezzanine • Gigabit Ethernet control and data link • 4 positions for dual STiC mezzanines • SPI and I2C control interfaces on board • DSUB 9 for Bias voltage distribution • Light injection mezzanine • 4x Fast ctrl connection with RJ45

  8. Clock Fan-Out on DAQ board • System clock 160MHz selectable from RJ45 connector (LVDS) or local oscillator • For example IDT 8SLVD1204-33 2 input 4 output $3 • One for system clk generator input to delay chip • 3x for RJ45 output • Delay fast control signals to align system timing, 10ns possible before system clock is fan out • Clock, Reset, Trig MC100EP195 $12 • System clock multiplication frequency x 4 • LMK03033C 2x 160MHz 2x 622MHz (one to FPGA one to clock fan-out for STiC boards $20 • Clock fan-out 2:4 for system clock and TDC clock • For example with two IDT 8SLVD1204-33 $3 • Implement level conversion with FPGA to exit LVTTL signals for debugging • On STiC board use clock fan-out chip to get 4 TDC clocks and 2 System clocks IDT 8SLVD1204-33

  9. STiC signals

  10. Readoutscheme of the STiC chip

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