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Exam Review of Cache Memories Dec 11, 2001

Exam Review of Cache Memories Dec 11, 2001. 15-213 “The course that gives CMU its Zip!”. Topics Cache memory organization Cache analysis of C code. Sanjit A. Seshia. Associativity E = 1 for direct mapped. Set bits = s = log(S). Block offset bits = b = log(B).

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Exam Review of Cache Memories Dec 11, 2001

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  1. Exam Review ofCache MemoriesDec 11, 2001 15-213“The course that gives CMU its Zip!” • Topics • Cache memory organization • Cache analysis of C code Sanjit A. Seshia

  2. Associativity E = 1 for direct mapped Set bits = s = log(S) Block offset bits = b = log(B) General organization of a cache memory A cache of size C contains S sets each of which has E cache blocks each of which has B bytes m bits for Addressing #(tag bits) = t = m – (s+b) C = E x S x B

  3. Therefore, E = 1 S = 16K = 2^14 Cache Analysis • Problem from Fall 1999 Final Exam (also Homework probs 6.28--6.30 in the textbook) Consider the following system: Direct mapped cache Cache size, C = 64Kbytes Block size, B = 4 bytes struct pixel { char r; char g; char b; char a; } struct pixel buffer[480][640]; register int i, j; register char *cptr; register int *iptr; • Assumptions: • sizeof(char) == 1, • sizeof(int) == 4 • buffer begins at address 0 • Cache is initially empty • All other variables are in registers

  4. A “write” is a write to a C variable of a primitive data type. For pointers, the size of the target location depends on the pointer type. Cache Analysis(contd) struct pixel { char r; char g; char b; char a; } struct pixel buffer[480][640]; register int i, j; register char *cptr; register int *iptr; Code is just scanning the entire array once for(j=0; j < 640; j++){ for(i=0; i < 480; i++){ buffer[i][j].r = 0; buffer[i][j].g = 0; buffer[i][j].b = 0; buffer[i][j].a = 0; } } What percentage of writes in this code will miss?

  5. ………. buffer j i Cache Block: r g b a order of access Cache Analysis(contd) struct pixel { char r; char g; char b; char a; } struct pixel buffer[480][640]; register int i, j; register char *cptr; register int *iptr; for(j=0; j < 640; j++){ for(i=0; i < 480; i++){ buffer[i][j].r = 0; buffer[i][j].g = 0; buffer[i][j].b = 0; buffer[i][j].a = 0; } } What percentage of writes in this code will miss?

  6. ………. buffer j i Cache Block: r g b a Cache Analysis(contd) struct pixel { char r; char g; char b; char a; } struct pixel buffer[480][640]; register int i, j; register char *cptr; register int *iptr; for(j=0; j < 640; j++){ for(i=0; i < 480; i++){ buffer[i][j].r = 0; MISS buffer[i][j].g = 0; HIT buffer[i][j].b = 0; HIT buffer[i][j].a = 0; HIT } } What percentage of writes in this code will miss? order of access

  7. ………. buffer j i Cache Analysis(contd) struct pixel { char r; char g; char b; char a; } struct pixel buffer[480][640]; register int i, j; register char *cptr; register int *iptr; for(j=0; j < 640; j++){ for(i=0; i < 480; i++){ buffer[i][j].r = 0; MISS buffer[i][j].g = 0; HIT buffer[i][j].b = 0; HIT buffer[i][j].a = 0; HIT } } What percentage of writes in this code will miss? ANS: 25 % of writes will miss

  8. Accesses the array in Row-major order Cache Analysis(contd) struct pixel { char r; char g; char b; char a; } struct pixel buffer[480][640]; register int i, j; register char *cptr; register int *iptr; cptr = (char *) buffer; for(; cptr < ((char *) buffer) + 640*480*4; cptr++){ *cptr = 0; } What percentage of writes in this code will miss?

  9. j i Cache Analysis(contd) struct pixel { char r; char g; char b; char a; } struct pixel buffer[480][640]; register int i, j; register char *cptr; register int *iptr; ………. buffer cptr = (char *) buffer; for(; cptr < ((char *) buffer) + 640*480*4; cptr++){ *cptr = 0; } What percentage of writes in this code will miss? Still 25% (previous analysis still holds)

  10. Cache Analysis(contd) struct pixel { char r; char g; char b; char a; } struct pixel buffer[480][640]; register int i, j; register char *cptr; register int *iptr; iptr = (int *) buffer; for(; iptr < ((int *) buffer) + 640*480; iptr++){ *iptr = 0; } What percentage of writes in this code will miss?

  11. j i Cache Analysis(contd) struct pixel { char r; char g; char b; char a; } struct pixel buffer[480][640]; register int i, j; register char *cptr; register int *iptr; “grouped” into an int ………. Same access pattern as cptr case, but ¼ times as many writes! iptr = (int *) buffer; for(; iptr < ((int *) buffer) + 640*480; iptr++){ *iptr = 0; }

  12. Cache Analysis(contd) iptr = (int *) buffer; for(; iptr < ((int *) buffer) + 640*480; iptr++){ *iptr = 0; } What percentage of writes in this code will miss? 100% of writes will miss

  13. Summary • For more problems: • See homework problems at the back of Chapter 6 • Cache problems on previous exams • These slides will be available on the “lectures” • webpage.

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