Logic Decomposition of Asynchronous Circuits Using STG Unfoldings

1. Logic Decomposition of Asynchronous Circuits Using STG Unfoldings Victor Khomenko School of Computing Science, Newcastle University, UK

2. Asynchronous circuits • The traditional synchronous (clocked) designs lack flexibility to cope with contemporary design technology challenges Asynchronous circuits – no clocks: • Low power consumption and EMI • Tolerant of voltage, temperature and manufacturing process variations • Modularity – no problems with the clock skew and related subtle issues [ITRS’09]: 22% of designs will be driven by ‘handshake clocking’ in 2013, and 40% in 2020 • Synthesis algorithms are complicated • Computationally hard to synthesize efficient circuits

3. Motivation • Logic decomposition is one of the most difficult tasks in logic synthesis • The quality of the resulting circuit (in terms of area and latency) depends to a large extent on the way logic decomposition was performed

4. F instant evaluator delay … Speed-independency assumptions • Gates are atomic (so no internal hazards) • Gates’ delays are positive and unbounded (and perhaps variable) • Wire delays are negligible (SI) or, alternatively, wire forks are isochronic (QDI)

5. delay delay delay delay G H1 … … Hk … Speed-independent decomposition F instant evaluator …

6. Data Transceiver Device Bus d lds dtack- dsr+ lds+ csc+ dsr VME Bus Controller ldtack dtack d- lds- ldtack- ldtack+ csc- dsr- dtack+ d+ VME Bus Controller

7. May be not in the gate library and has to be decomposed Complex-gate implementation Data Transceiver Device Bus d lds dtack dsr csc ldtack

8. Unexpected! Unexpected! Naïve decomposition is hazardous dtack- dsr+ lds+ csc+ d- lds- ldtack- ldtack+ csc- dsr- dtack+ d+ d lds dtack dsr csc x ldtack

9. Insert a new signal dec whose implementation is [dec] = ldtack + csc Decompose at the PN level! dtack- dsr+ lds+ csc+ ldtack+ d- lds- ldtack- dec+ dec- csc- dsr- dtack+ d+ d lds dtack Multiway acknowledgement dsr csc dec ldtack

10. d lds dtack dsr csc ldtack d lds dtack C dsr csc ldtack Latch utilisation Only possible because there is no globally reachable state at which dsr=ldtack=0 and csc=1

11. State Graphs vs. Unfoldings State Graphs: • Relatively easy theory • Many algorithms • Not visual • State space explosion problem

12. State Graphs vs. Unfoldings Unfoldings: • Alleviate the state space explosion problem • More visual than state graphs • Proven efficient for model checking • Quite complicated theory • Not sufficiently investigated • Relatively few algorithms

13. Function-guided signal insertion Logic decomposition algorithm forever do for all non-input signals x do S[x] ← ∅ for all G  {latches, gates} do S[x] ← S[x]  decompositions(x,G) bestH[x] ← best SI candidate in S[x] if for each x, bestH[x] is implementable Library matching stop if for each x, bestH[x]=UNDEFINED fail H ← the most complex bestH Insert a new signal z implementing H into the STG [Cortadella et al, ’99]

14. Function-guided signal insertion Problem: given a Boolean function F, insert a new signal dec(i.e. a set of new transitions labelled dec+or dec-) with the implementation [dec]=F into the STG. Only unfolding prefix (rather than state graph) may be used.

15. Previous work: Transformations [PN’07] Sequential pre-insertion Sequential post-insertion Concurrent insertion

16. Previous work: main results [PN’07] • Validity criteria: safeness & bisimilarity • can be checked before the transformation is performed, i.e. on the original prefix (to avoid backtracking) • Perform the insertion directly on the prefix • avoid re-unfolding • good for visualization (re-unfolding can dramatically change the look of the prefix) • Can transfer some information between the iterations of the algorithm • The suite of transformations is good in practice for resolution of encoding conflicts

17. Motivation for more transformations The suite of transformations is not sufficient for logic decomposition; intuitively: only linear (in the PN size) number of sequential pre- and post-insertions (assuming that the pre- and postset sizes are bounded) only quadratic (in the PN size) number of concurrent insertions exponential number of ‘cuts’ in the PN where a Boolean expression can change its value

18. Example: imec-sbuf-ram-write dec+ imec-sbuf-ram-write prbar req wen precharged wsen done ack wsldin wsld wenin dec- Implementation of prbar: (csc2 req)  csc1  wsldin dec

19. Generalised transition insertion [ICGT’10] s1 d1 sources s2 destinations d2 s3 • All previously listed good points hold for GTIs as well  • Exponentially many GTIs can exist: • more likely that an appropriate transformation exists  • no longer practical to enumerate them all  • can enumerate only the ‘potentially useful’ (for logic decomposition) GTIs 

20. x I C F=v F=v Compatible insertions An insertion I is compatible with F if whenever an x can fire and trigger I, F’x=1, where F’x= Fx=0  Fx=1 Intuitively, when x fires, the value of F must change, as I becomes enabled.

21. Compatible insertions F=0 dtack- dsr+ csc+ dsr+ lds+ ldtack+ dtack+ csc+ csc- d+ dsr- d- lds- ldtack- F=1 F=1 F =ldtack csc

22. [ACSD’07] Reduction to (incremental) SAT Find an optimal w.r.t. a heuristic cost function SAT assignment of the Boolean formula MUTEX SA  CUTOFF  FUN depending on the variables I1, ..., Ik corresponding to the compatible insertions, and conveying that: • no two insertions are non-commuting, or concurrent, or in auto-conflict, or one of them can trigger the other (MUTEX) • consistent assignment of signs is possible in the prefix (SA) and beyond cut-offs (CUTOFF) • F is a possible implementation of the newly inserted signal (FUN)

23. Cost function Parameterised by the user; takes into account: • the delay introduced by the insertion • the number of syntactic triggers of all non-input signals • the number of inserted transitions of a signal • the number of signals which are not locked with the newly inserted signal • …

24. x I C F=v F=v Building FUN Let C be a configuration enabling some x, F’x=1, and I be the set of compatible insertions such that: Then the clause VII I is in FUN. One can build a Boolean formula FUNGEN depending on C and compatible insertions whose SAT assignments satisfy this condition.

25. Building FUN (cont’d) Problem: it is infeasible to enumerate all configurations. Idea 1: The same clause can be generated by many different configurations, and hence once one such configuration is found, the others can be excluded from the search. Idea 2: Clauses subsumed by already generated ones can be excluded from the search. It is enough to add a clause VIII to FUNGEN whenever a new clause VII I is computed.

26. C C Building FUN (example) F=0 dtack- dsr+ csc+ dsr+ lds+ ldtack+ dtack+ csc+ csc- d+ dsr- d- lds- ldtack- F=1 F=1 F =ldtack csc

27. Experimental results • Implemented in MPSAT (library matching not implemented yet) and compared with PETRIFY • Assorted small benchmarks: • Similar failure rates and the quality of circuits  • structural insertions seem sufficient  • The tests reflect the quality of heuristics in choosing the decomposition in each step rather than the quality of the signal insertion routine  • Large benchmarks • Tend to be non-decomposable by both tools  • Only one series (scalable pipelines) was useful • can be solved by a single insertion, hence minimizes the impact of heuristics and reflects the quality of the signal insertion routine • huge reachability graphs, so unfoldings win 

28. Conclusions • Unfolding-based decomposition algorithm • alleviates state space explosion • completes the design cycle based fully on unfoldings (i.e. state graphs are never built) • All advantages of state-based decomposition are retained: • multiway acknowledgement • latch utilisation • highly optimised circuits

29. Thank you! Any questions?