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Computer Architecture: Intro Anatomy of a CPU

Computer Architecture: Intro Anatomy of a CPU. J. Schmalzel S. Mandayam. Objectives, 1.  Describe major functional elements of CISC, RISC architectures Perform detailed analysis and synthesis of combinatorial and sequential subsystems using schematic and/or behavioral design capture w/ sim

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Computer Architecture: Intro Anatomy of a CPU

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  1. Computer Architecture: Intro Anatomy of a CPU J. Schmalzel S. Mandayam

  2. Objectives, 1  Describe major functional elements of CISC, RISC architectures • Perform detailed analysis and synthesis of combinatorial and sequential subsystems using schematic and/or behavioral design capture w/ sim • Describe principles and applications of the three basic computing elements: CPU, MEM, I/O • Use an embedded system that includes diverse architectural features

  3. Objectives, 2 Apply analytic and simulation techniques to predict and verify performance metrics  Design an example architecture using SOTA tools • Identify opportunities for hardware and software trade-offs • (Insert your objectives here…) • ( …and here)

  4. CPU MEM I/O Hierarchical View of EP and Digital Systems Operating System HLLs Computer Architecture State Machines Interface Method Design Techniques MSI Functions Boolean Algebra Gates

  5. Central Processing Unit (CPU) • Controls • Executes • Computes (Fixed- and/or Floating-Point)

  6. Small footprint 25.8 MHz CPU 40 CMOS-compatible parallel I/O lines Four CMOS-compatible serial ports; max async rate of 806 kbps, max sync rate of 6.45 Mbps 8-bit data bus 13 address lines Control signals (I/O read, write) Master/slave config Reset input, output 5, 8-bit and 2, 10-bit timers 256K flash EPROM, 512KB SRAM RTC Status, WDT outputs Example EP Feature List

  7. What’s Implied by Feature List? • Tight confederation of functional elements • Ability to control and sequence operations • Well-defined interfaces to external memory and I/O A sample EP architecture looks like…

  8. BlockDiagram

  9. What about the CPU? • The previous block diagram emphasized the collection of I/O and control resources • One step closer on the abstraction scale is to look at the programmer’s model of the CPU

  10. CPU Register Set (“Programmer’s Model”)

  11. Program Counter Address Unit Instruction Register Instruction Decoder Register File Control/Timing Function Unit (ALU) Floating Point Unit (FPU) Status Register Stack Register Index Register Internal CPU Architecture

  12. Concept of CPU as Two Paths • Data Path • Where data elements flow from/to • Where operations are performed • Control Path • The source of data path control

  13. Simple Model Data Path (7-18) Dbus W n-bit bus Register File Dadd Signal Aadd Const MBsel MuxB Aout Dout FS Function Unit Status Din MDsel MuxD Dbus

  14. Instruction Word DA AA BA MB FS MD RW

  15. The way the EP computes and performs operations Load registers Immediate Memory Indexed Register-to-Register Exchange Registers Stack Operations 8- and 16-bit Arithmetic and Logical Operations Bit Set, Reset, Test Increment/Decrement Shifts and Rotate Block Moves Program Flow Control Fast A Instructions Control Privileged Instructions Miscellaneous (e.g. NOP) Instruction Set

  16. Questions, Comments, Discussion

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