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by Dr. K.K.Thyagharajan, M.E., Ph.D. Professor Department of Information Technology

Microprocessors and Microcontrollers. by Dr. K.K.Thyagharajan, M.E., Ph.D. Professor Department of Information Technology R.M.K. Engineering College Websites: www.tansitresearch.org www.geocities.com/kkthyagharajan/ Email: kktflashtraining@yahoo.co.in.

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by Dr. K.K.Thyagharajan, M.E., Ph.D. Professor Department of Information Technology

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  1. Microprocessors and Microcontrollers by Dr. K.K.Thyagharajan, M.E., Ph.D. Professor Department of Information Technology R.M.K. Engineering College Websites: www.tansitresearch.org www.geocities.com/kkthyagharajan/ Email: kktflashtraining@yahoo.co.in

  2. Address Decoding And Memory Mapping • Memory address decoding is nothing but to assign an address for each location in the memory chip. • Memory address can be decoded in two ways • Absolute or Fully decoding • and • 2. Linear Select or Partial decoding

  3. Absolute or Fully Decoding • ADVANTAGES • Each memory location has only one address, there is no duplication in the address • Memory can be placed contiguously in the address space of the microprocessor • Future expansion can be made easily without disturbing the existing circuitry DISADVANTAGES • Extra decoders are necessary • Some delay will be produced by these extra decoders.

  4. 216 different addresses from 0000H to FFFFH so that each location in the memory will have a unique address as shown below

  5. 64KB Memory Map (Single Block)

  6. 64KB Memory Map(Eight Blocks)

  7. Memory Block Decoder

  8. Linear Select or Partial Decoding • ADVANTAGES • Simplified decoding circuit • Reduced the hardware design cost • DISADVANTAGES • Multiple addresses are provided for the same location • Complete memory space of the microprocessor is not efficiently used • Adding or interfacing ICs with already existing circuitry is difficult.

  9. Linear Select Address Decoding Circuit Diagram Chip Select Signals

  10. The same EPROM is selected both for the address range 0000H to 1FFFH and 8000H to 9FFFH.

  11. Bus Contention Reading Opcode from the Memory

  12. Avoiding Bus Contention

  13. Interfacing low speed memory

  14. Wait State Generator

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