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Physikalisch-Technische Bundesanstalt, Braunschweig

Application of phase shifters in superconducting digital circuits. M. Khabipov , D. Balashov, F. Maibaum, A. Zorin Physikalisch-Technische Bundesanstalt, Bundesallee 100, 38116 Braunschweig, Germany V. A. Oboznov, V. V. Bolginov, A.N. Rossolenko and V. V. Ryazanov

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Physikalisch-Technische Bundesanstalt, Braunschweig

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  1. Application of phase shifters in superconducting digital circuits M. Khabipov, D. Balashov, F. Maibaum, A. Zorin Physikalisch-Technische Bundesanstalt, Bundesallee 100, 38116 Braunschweig, Germany V. A. Oboznov, V. V. Bolginov, A.N. Rossolenko and V. V. Ryazanov Institute of Solid State Physics, Chernogolovka, 142432 Moscow region, Russia The work was supported by DFG (German Science Foundation) through grant ZO124/2-1 and the joint grant of DFG and the Russian Foundation of Basic Researches and grants of the Russian Academy of Sciences. Physikalisch-Technische Bundesanstalt, Braunschweig

  2. Outline • Introduction • Basic principles of Rapid Single Flux Quantum (SFQ) circuits • SFQ circuits fabrication technology at PTB • Operation of an SFQ circuits with integrated phase shifters based on • superconducting loop with trapped flux quantum • Superconductor-Ferromagnetic-Superconductor p-junction • Conclusion • Outlook

  3. w 2 p 2  = c ICR2C= w 2 c F p 0 RSJ model of Josephson tunnel junction V JJ JJ - Josephson junction C – self-capacitance C R damping resistor I Stewart-McCumber parameter Underdamped JJ Overdamped JJ I I Ic Ic IReturn 0 <V> IReturn C 1 C >> 1 <V> 0

  4. R I Reaction on a short pulse I(t) Ic “sweep” of the dc I-V curve Idc bias a short trigger pulse <V> a few Ohm V(t) Generation of a SFQ pulse (strictly 2p-leap of phase!) Result: time This pulse (carrier of information) can be used as a trigger pulse for other junctions - the basis of Rapid Single Flux Quantum circuits! (Likharev et al. 1985) Advantages of RSFQ: quantized information, fast (typically, few ps) switching time, low level of dissipation

  5. R SFQ pulse generation  move to the adjacent minimum U(j) = - EJcosj- (0/2)  I +const  effect of the trigger pulse! large damping due to external shunt resistor washboard potential Low amplitude signals (noise) not reproduced by the circuit a noise discriminator 2p j

  6. Definition of coding in RSFQ logic clock pulses V/Vc „0“ „1“ „0“ information pulse V/Vc V/Vc „0“ „0“ „1“ information pulse Time, a. u. The binary code: presence (absence) of SFQ pulse between adjacent clock SFQ pulses (for comparison) different voltage levels (CMOS, TTL, “latching” logic)

  7. I _b I _in L 1 J 2 0 J 1 9 J 2 L i n L 2 I _ L J 1 8 J 1 J 1 7 J 3 J 4 J 5 J 2 1 J 2 3 J 2 2 R V J 2 4 _out RSFQ dc/SFQ and SFQ/dc converter circuit Circuit provide generation and back conversion of SFQ pulses into voltage signals T-Flipflop with SFQ/dc converter dc/SFQ converter Josephson transmission line V. Kaplunenko et al. IEEE Trans. Magnetics25, 861-864, 1989 K. Likharev and V. Semenov IEEE Trans. Appl. Supercond. 1, 3-28, 1991

  8. RSFQ T-flip-flop circuit Circuit provides a frequency division of SFQ pulses Ibias  As result frequency division ! jc = 100 A/cm2 operation frequency f = Vc /Ф0 =Ic Rn/Ф0 up to 40 GHz power consumption P = V Ibias= 15 nW K. Likharev and V. Semenov IEEE Trans. Appl. Supercond.,1, 1991

  9. T-flip-flop circuit, results of simulation Phase drop, input junction Phase drop, TFF junctions Voltage, input junction Voltage, TFF junction Voltage, TFF junction

  10. Frequency division realised in CMOS logic(for comparison) Paul Horowitz, Winfield Hill. The Art of Electronics, Cambridge University Press, Second Edition, 1989 Pdyn = CeffV2DDxf For example, at 30fF/gate at 100MHz and VDD = 5 V, 75 μW is dissipated per gate UMBC, University in Mariland, Advanced VLSI design http://www.csee.umbc.edu . The circuit consists of 10 gates and includes about 50 transistors

  11. SFQ circuits Nb/Al thin-films fabrication technology established at PTB -deposition and etching of The Nb ground plane Shielding of an electromagnetic noise, realization of the low value inductances • anodization of the ground plane - deposition of the SiO2 isolation layer - deposition and etching of the Cr/Pt/Cr resistor trilayer - deposition of the SiO2 isolation layer - etching of the contact holes realization of the shunt and bias current resistors -deposition of the Nb/AlxOy/Nb trilayer -deposition of a thin SiO2 layer jc between 100 A/cm2 and 1 kA/cm2

  12. SFQ circuits Nb/Al thin-films fabrication technology established at PTB -etching of the thin SiO2 isolation layer and the Nb counter electrode, definition of JJs Smallest junction area A=10 µm2 -anodization with the thin SiO2 layer as a mask -etching of the base electrode -deposition and etching of the SiO2 isolation layer

  13. Cross-section of shunted Josephson junction in Nb/Al technology JJ Nb Tunnel barrier AlxOy Al O 2 3 Al Cr/Pt/Cr damping resistor Rsq=2Ω/sq. Cr/Pt/Cr } Thermally oxidized silicon substrate Nb O 2 5 SiO 2 IV curve of the underdamped JJ IV curve of the overdamped JJ Si C>>1 C ~ 1 A= 24 µm2 Ic  20 µA Rn  59 Ω A= 24 µm2 Ic  24 µA Rsh  4 Ω (100µV/div) (1mV/div) Rsh   JJ Voltage V Voltage V IC IR IC T = 4.2 K T = 4.2 K Current I (20µA/div) Current I (20µA/div)

  14. Why we need phase shifting elements in RSFQ? Qubit control and read out: low back action on Josephson qubit cells (low value Ic, large value of shunt resistor, low power consumption) Low Ic value due to Ic x L~Ф0 result in proportionally increased value of inductancesL, circuits have a large area and became sensitive to an electromagnetic noise Physikalisch-Technische Bundesanstalt, Braunschweig

  15. 0 p-JJ Conventional TFF with large storing inductance Symmetry of the TFF states is due to phase drop of about p created by dc control current: Icontr L j =p Compact phase shifters are required SFS L Superconducting loop with trapped flux quanta TFF with RC shunted Josephson junctions. Parameters: jc=100 A/cm2, Ic= 16µA, L=130 pH The p shiftcan also be realized on the basis of HTS junctions exhibiting the d-wave symmetry of the order parameter (see T. Ortlepp et al. Science 312, 1495, 2006)

  16. Superconducting loop with trapped flux quantum as a phase shifting element The work carried out in collaboration with the group in TU Ilmenau f = π I shifter I shifter T = 10 K T = 4.2 K External flux  applied at T > TC Nb (T = 10 K) External flux  turned of when T < TCNb (liquid helium temperature T = 4.2K). Quantized flux trapped trapped = n  00  2.07 mVps (single flux quantum) trapped = n  0 Flux quantization law It was proposed as a phase-bias circuit for the Josephson qubit in J.B. Majer et al. APL 80, 3638, 2002.

  17. Superconducting loop with trapped flux quantum as a phase shifting element The work carried out in collaboration with the group in TU Ilmenau Pinning a flux quanta into ground plane hole During the cooldown, the flux is trapped in the ground plane hole.

  18. Conventional TFF and TFF with integrated π – shifter Schematic diagram of the ordinary TFF circuit Schematic diagram of the TFF with integrated -shifter TFF input TFF input J1 J2 J1 J2 Lint TFF out1 TFF out2 TFF out1 TFF out2 Lshifter J4 J3 J4 J3 The large quantizing inductance Lint can be replaced by passive π – shifter, ensuring bistable functioning of the TFF D. Balashov et al., IEEE Trans. Appl. Supercond.17, 142,2007

  19. Simpler circuit:dc-interferometer with integrated π–shifter dc-interferometer with integrated π – shifter Microphotograph of the sample Ibias Vout Ibias Vout -shifter Isweep Isweep Isweep Isweep JJ JJ  + J1 J2 Control line Circuit parameters: IC  270 µA, RN  0.8 , Lshifter  7 pH (at T=4.2K), and Lshifter 15 pH (at T=10K), Flux bias current for single 0 operation mode  Icontr  200 µA

  20. Ibias Vout Isweep Isweep J1 J2 Experimental testing of the dc-interferometer with integrated π–shifter Voltage-flux characteristics of the dc-interferometer with integrated shifter loop realized in jC=1 kA/cm2 Nb/Al technology 0  No flux trapped in the shifter loop Icontr  0 µA V (20 µV/div) 0/2  1 0 trapped in the shifter loop Icontr  200 µA Flux  Current Isweep ( 200 µA/div) Voltage-flux characteristics

  21. TFF circuit with integrated π–shifter Microphotograph of the sample Schematic diagram of the TFF with integrated -shifter TFF input TFF separate bias TFF input -shifter J2 J1 TFF out-1 TFF out-2 TFF out-1 TFF out-2 Lshifter  + J3 J4 Control line

  22. Block-diagram of tested circuit including TFF with integrated π – shifter -shifter I_in (Divider 2:1) (Divider 2:1)  + V_out2 V_out1 Control line TFF with -shifter should operate as a frequency divider 2:1

  23. Experimental testing of the circuit with integrated π–shifter Circuit realized in Nb/Al technology withjC=1k A/cm2 I_in When no flux trapped in the π – shifter loop fout1 = fout2= fin/2 Bias current margin of the circuit is  20%  Current (500 µA/div) Voltage (200 µV/div) V_out1 V_out2 I_in When 0trapped in the π – shifter loop fout1 = fout2= fin/4 Bias current margin of the circuit is  17%  V_out1 V_out2 Time t( 5 ms/div)

  24. I  I  E E   p-junction as a phase inverting element Josephson current-phase relation π-junction current- phase relation Symbolic notation  p-JJ  I=Icsin 2 I=Icsin[+]= -Icsin  2  E= EJ[1-cos] E= EJ[1-cos(+)]=EJ[1+cos]  -  - 0 -junction energy minimum at  0-junction energy minimum at 0 Bulaevsky, Kuzii and Sobyanin, JETP Lett. (1977)

  25. -junction Superconductor-Ferromagnet-Superconductor (SFS) junction: 0-state and π–state Nb-Cu0.47Ni0.53-Nb “0”-state I=Icsin “0”-state I=Icsin dF = 12-22 nm “”-state I = Icsin(+) = - Icsin() V. A. Oboznov et al. PRL 96, 197003, 2006

  26. Cross-section of shunted Josephson junction in Nb/Al technology and ferromagnetic based junction SIS-junction jc=100 A/cm2 A = 10 µm2 SFS-junction jc=850 A/cm2 A = 8x8 µm2 Topologically, the SFS junction is placed between Nb-wiring nodes of pre-fabricated circuit.

  27. dc-interferometer with integrated SFSπ-junction Voltage-flux characteristics of the dc interferometers: a) conventional, b) with SFS p-junction

  28. Integration of the p- SFS junction into TFF circuit TFF with integrated π-SFS junction Conventional TFF circuit JJ JJ JJ JJ ∆=π π-SFS JJ JJ JJ JJ L Proposed in: A. Ustinov and V. Kaplunenko J. Appl. Phys. 94,5405,2003

  29. Integration of the p- SFS junction into TFF circuit Phase drop, input junction Phase drop, TFF junctions Voltage, TFF junction Voltage, TFF junction Voltage, p-junction operation ranges: jc =  32%, Ib=  40%, L=  50% p- junction substituted by fixed phase shift of p and junction having Ic of large value

  30. Microphotograph of integrated circuit V_out1 V_out2 SFS -junction JTL SFQ/dc JTL SFQ/dc TFF dc/SFQ I_in I_bias 50 µm SFQ pulses generated by dc/SFQ converter, processed by TFF with integrated p-SFS junction and converted to the voltage levels by SFQ/dc converter circuits

  31. TFF circuit with integrated SFS π–junction a) Block diagram of the test circuit b) microphotograph of the TFF circuit

  32. Proof of correct operation of TFF circuit with integrated SFS π–junction Circuit realized in Nb/Al technology with jC=100 A/cm2 When SFS junction is in a π–state then circuit operates properlyTout1 = Tout2= 4Tin Bias current margin of the circuit is  19% and limited by bias current margins of dc/SFQ converters!

  33. 0 p-JJ Conclusion • We have successfully integrated the phase shifting elements in RSFQ circuits without deep modification of currently available technological process. • The following phase shifting elements were experimentally studied: • superconducting ring with trapped flux quantum • SFS p-junctions

  34. Outlook Measurements of operation ranges of bias current of SFQ circuits with integrated SFS p-junctions - design of the TFF circuit with separate bias current Bit error rate (BER) measurements - realisation of the TFF circuit incorporated into ring oscillator

  35. Integration of the p- SFS junction into TFF circuit Schematic for the circuit simulation, operation ranges, jc =  32%, Ib=  40%, L=  50% p- junction substituted by fixed phase shift of p and junction having Ic of large value

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