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VLSI Testing

VLSI Testing. Design error and fault simulation. 304-649. Jean-François Boland. Presentation Plan. Project Overview Design error and fault models ESIM Software Future work. Project Overview. Simulation Design error Logical fault ESIM software, [Al-Asaad 00], [Hayes 00]

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VLSI Testing

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  1. VLSI Testing Design error and fault simulation 304-649 Jean-François Boland

  2. Presentation Plan • Project Overview • Design error and fault models • ESIM Software • Future work

  3. Project Overview • Simulation • Design error • Logical fault • ESIM software, [Al-Asaad 00], [Hayes 00] • Fault and design errors models • Algorithms use for faults/errors simulation • Experimental results and performances

  4. Error models Design error • Gate Substitution Errors (SIGSE, MIGSE) • 67% of all manual design errors • Gate Count Errors (EGE, MGE) • Input Count Errors (EIE, MIE) • Wrong Input Errors (WIEs) Fault error • Single Stuck-Line (SSL) • Input Pattern (IP)

  5. Examples of design errors

  6. ESIM Software Specifications • Written using C++ (open source) • Simulation algorithms for GP1 and GP2 errors • Uses the netlist format of the ISCAS-85 benchmark circuits. Application • Evaluate the coverage of design errors and logical faults of typical ATPG.

  7. Future work • GP1 and GP2 algorithms overview. • Performances and experimental results analysis. • ESIM functionality requirements. • Limits and improvements.

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