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PLDs, FPGAs, and Decoders

PLDs, FPGAs, and Decoders. Programmable Logic Arrays (PLAs). Any combinational logic function can be realized as a sum of products . Idea: Build a large AND-OR array with lots of inputs and product terms , and programmable connections . n inputs

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PLDs, FPGAs, and Decoders

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  1. PLDs, FPGAs, and Decoders

  2. Programmable Logic Arrays (PLAs) • Any combinational logic function can be realized as a sum of products. • Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections. • n inputs • AND gates have 2n inputs -- true and complement of each variable. • m outputs, driven by large OR gates • Each AND gate is programmably connected to each output’s OR gate. • p AND gates (p<<2n)

  3. Programmable Logic Arrays (PLAs) • A PLA is a combinational, two-level AND-OR device that can be programmed to realize any sum-of-products logic expression, subject to the size limitations of the device. • Limitations are: • the number of inputs (n) • AND gates have 2n inputs -- true and complement of each variable. • the number of outputs (m), driven by large OR gates • Each AND gate is programmably connected to each output’s OR gate. • the number of product terms (p AND gates; p<<2n)

  4. Programmable Logic Arrays (PLAs) • Such a PLA is described as n x m PLA with p product terms an n x m PLA with p product terms contains: p 2n-input AND gates and m p-input OR gates. e.g., 4 x 3 PLA with 6 product terms an 4 x 3 PLA with 6 product terms contains: 6 8-input AND gates and 3 6-input OR gates.

  5. Example: 4x3 PLA, 6 product terms

  6. Compact representation • Actually, closer to physical layout (“wired logic”).

  7. Some product terms

  8. PLA Electrical Design • A 4 x 3 PLA built using diode logic.

  9. PLA Electrical Design • A 4 x 3 PLA built using TTL-like open-collector gates.

  10. PLA Electrical Design • By applying special input patterns to the device, it is possible to select individual links, apply a high voltage (10-30 v), and thereby vaporize selected links.

  11. PLA Electrical Design • Instead of a diode, an n-channel transistor with a programmable connection is placed at each intersection between an input line and a word line. • Reduced power consumption • reprogrammability

  12. PLA Electrical Design • See Section 5.3.5 -- wired-AND logic

  13. Programmable Array Logic (PALs) • How beneficial is product sharing? • Not enough to justify the extra AND array • PALs ==> fixed OR array • Each AND gate is permanently connected to a certain OR gate. • Example: PAL16L8

  14. 10 primary inputs • 8 outputs, with 7 ANDs per output • 1 AND for 3-state enable • 6 outputs available as inputs • more inputs, at expense of outputs • two-pass logic, helper terms • Note inversion on outputs • output is complement of sum-of-products • newer PALs have selectable inversion

  15. EPLDs • An erasable Programmable Logic Device • can be reprogrammed and uses floating-gate MOS transistor.

  16. EPLDs

  17. CPLDs and FPGAs • CPLDs - complex PLDs use floating-gate programming technology. • FPGAs - Field-Programmable Gate Arrays use read/write memory cells to control the state of each connection.

  18. Designing with PALs • Compare number of inputs and outputs of the problem with available resources in the PAL. • Write equations for each output using ABEL. • Compile the ABEL program, determine whether minimimized equations fit in the available AND terms. • If no fit, try modifying equations or providing “helper” terms.

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