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Virtual Memory

Virtual Memory. HABEEB P. Virtual Memory. Memory management technique that is implemented using both hardware and software . It maps memory addresses used by a program, called virtual addresses , into physical addresses in computer memory.

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Virtual Memory

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  1. Virtual Memory HABEEB P

  2. Virtual Memory • Memory management technique that is implemented using both hardware and software. • It maps memory addresses used by a program, called virtual addresses, into physical addresses in computer memory. • Address translation hardware in the system, often referred to as a memory management unit or MMU, automatically translates virtual addresses to physical addresses • Paging provides a mechanism to implement virtual memory.

  3. Address Translation: An Overview Logical Address Linear Address Physical Address Physical Memory Translation Logical to Linear Translation Linear to Physical Segmentation Unit Paging Unit CPU

  4. Memory in Paging Virtual Address Space Physical Address Space 24575 Page Table LA to PA Mapping 20480 16383 20479 12288 16384 12287 16383 8192 12288 8191 12287 PA VA 4096 8192 4095 8191 What is the physical address for virtual address 300? 4096+300 0 4096 4095 0 4096-8191 0-4095

  5. Virtual Memory .. Without Virtual Memory With Virtual Memory Program Address Maps to RAM Address Program Address = RAM Address Program Address Space (4GB) Program Address Space (4GB) 1GB Physical Memory 1GB Physical Memory 0 1 2 … MAP 0 1 2 … Crash Disk

  6. Problems with Memory 1. What if we don’t have enough memory? • Let suppose a program need 4GB of memory. • Program can access any address in its 32-bit address space. • What if we don’t have 4GB of memory? 1GB Physical Memory Program Address Space (4GB) 0x00000000 Crash if try to access more than 1 GB 0xFFFF FFFF

  7. Problems with Memory .. 2. Holes in address space • Program 1 and Program 2 fit in the memory, and use 1+2 =3GB. • Quit Program 1 • Can`t run program3 even though we have enough Memory Program1(1GB) 0x00000000 Program2(2GB) Program3(2GB) 32 bit physical Address Space (4GB) 0xFFFF FFFF

  8. Problems with Memory .. 3. How do we keep programs secure? • Each program can access any address in RAM. Program 1 store bank balance at 2048 Program 2 store game score at 2048 They corrupt or crash each other Write 4000 to address 2048 40000 4000 Program1(1GB) 0x00000000 Program2(2GB) Write 40000 to address 2048 32 bit physical Address Space (4GB) 0xFFFF FFFF

  9. Memory Management Overview • The memory management facilities of the IA-32 architecture are divided into two parts • Segmentation • Segmentation provides a mechanism of isolating individual code, data, and stack modules. • Each program divided into segments. Each segment can have different size. • Paging • Paging provides a mechanism for implementing a conventional demand-paged, virtual-memory system where sections of a program’s execution environment are mapped into physical memory as needed. • Paging can be used to provide isolation between multiple tasks.

  10. Memory Management Overview.. • When operating in protected mode, some form of segmentation must be used. • There is no mode bit to disable segmentation. • The use of paging, however, is optional (If CR0.PG = 0, paging is not used. The logical processor treats all linear addresses as if they were physical addresses.)

  11. PAGING • Intel-64 processors support three different paging modes • 32-bit paging(CR0.PG = 1 and CR4.PAE = 0). • PAE paging (CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 0). • IA-32e paging (CR0.PG = 1, CR4.PAE =1, and IA32_EFER.LME= 1)

  12. PAGING.. • The three paging modes differ with regard to the following details • Linear-address width. • Physical-address width • Page size • Support for execute-disable access rights.

  13. PAGING.. Properties of Different Paging Modes

  14. PAGING.. • Enumeration of Paging Features by CPUID • Software can discover support for different paging features using the CPUID instruction

  15. 32-BIT PAGING • Although 40 bits corresponds to 1 TByte, linear addresses are limited to 32 bits; at most 4 GBytes of linear-address space may be accessed at any given time. • CR3 is used to locate the first paging-structure, the page directory.

  16. Linear-Address Translation to a 4-KByte Page using 32-Bit Paging Src: [1]

  17. Linear-Address Translation to a 4-KByte Page using 32-Bit Paging .. 31 22 21 12 11 0 Directory Table Offset Linear Address 39 39 32 32 31 31 12 12 11 11 2 2 1 1 0 0 0 … 0 0 … 0 PDE (31:12) CR3 (31:12) LA (31:22) LA (21:12) 00 00 PTE Address PDE Address 31 31 0 0 PDE CR3 PDE Address Calculation PTE Address Calculation

  18. Linear-Address Translation to a 4-KByte Page using 32-Bit Paging .. 31 22 21 12 11 0 Directory Table Offset Linear Address 39 32 31 12 11 0 0 … 0 PTE (31:12) LA (11:0) 4KB Page 31 0 PTE Final Physical Address Calculation Physical Memory

  19. 32-BIT PAGING • If CR4.PSE = 1 and the PDE’s PS flag is 1, the PDE maps a 4-MByte page • PSE: page-size extensions • If CR4.PSE = 0 or the PDE’s PS flag is 0, a 4-KByte naturally aligned page table • A page directory comprises 1024 32-bit entries (PDEs). Page Directory Page Table

  20. HIERARCHICAL PAGING STRUCTURES • Paging structures are used to translate linear address to physical. • PML4 • PDPT • PD • PT • All three paging modes translate linear addresses use hierarchical paging structures.

  21. Why Hierarchical Paging? • For 32 bit Machine with 4KB pages we need • 1 Million Page Table Entries • ( 32 Bit - 20 bit page offset = 20bit ; 220 = 1M) • Each Page Table entry is about 4 Byte • (20 bit for physical page + Permission bits ) • Total 4MB for each program • If we have 100 programs running then, we need 400MB of page tables!!!. • We cant swap page tables out of RAM (because only one level)

  22. Why Hierarchical Paging? • Two Level Paging Second Level 4KB Each (1024 PTEs) First Level 4KB Page (1024 PTEs) 0x0004 0x0100 0x0304 0x0304 0x0004 0x0204 0x0106 0x0006 0x0306 0x0206 0x0306 0x0006 Disk Disk Disk Disk Disk Disk Disk Disk Disk Disk Disk Disk 0x00AA 0x00AA 0x00AA 0x03AA 0x03AA 0x00AA ------ ---------- ---------- ---------- ---------- ---------- Physical Memory

  23. Why Hierarchical Paging? • With two level page table, what is the smallest amount of data need to keep in memory for each program? • 4KB+4KB • We always need first level page table so we can find second level pages. • We need at least one second level page table to start execution of the program. • If we have 100 programs in memory then, how much memory needed for page tables? • 800KB

  24. Virtual Memory: Solving Problem1 • Not enough RAM in the system • Map some of the program`s address space to the disk • When it need, bring to memory. 1GB Physical Memory Program Loads Address 0 VM map address 0 to ram1 Program Address Space (4GB) VM map address 1 to ram0 Program Loads Address 1 1 VM map address 3 to ram 2 2 0 0 3 Program Loads Address 3 MAP 1 3 2 Program Loads Address 2 2 • Page Fault • Replace Physical memory frame with new vale • Update Map Disk

  25. Virtual Memory: Solving Problem2 • Holes in address space • We can map program`s address space into RAM as we like. Program Address Space (4GB) MAP 2 • Can Map different virtual pages to different physical pages Program2(2GB) Program3(2GB) MAP

  26. Virtual Memory: Solving Problem3 • Keep Program Secure • Two programs map same virtual address to different physical address Write 4000 to address 2048 MAP1 Program 1 store bank balance at 2048 Program 2 store game score at 2048 Map VA 2048 To PA X 4000 Program1(1GB) Program2(2GB) MAP2 Map VA 2048 To PA Y 40000 Write 40000 to address 2048 32 bit physical Address Space (4GB)

  27. Program Address Space in Linux 32 bit Program virtual address space (4GB) 0x FFFF FFFF Kernel Space • Each program has its own 32-bit address space • 1GB Upper memory reserved for kernel • Stack grows down • Heap grows up • Random offset to enhance security • Data: static variables • Text : Program Binary 0x 0C00 0000 Random offset Stack Random offset Libraries Heap Random offset Data Text 0x 0000 0000

  28. Program Address Space in Linux.. Kernel Space Kernel Space Stack1 Shared Libraries Stack Stack Library 1 Program1 Virtual Address Space Heap1 Libraries Libraries Stack 2 Kernel Space Heap Heap Each Process use its own page tables Data Data Example Physical Address Space Program2 Virtual Address Space Text Text

  29. How Linux Manages Address Space strart_stack mmap_base Stack (grows down) Heap (grows up) Libraries (Memory Mapping Segment) task_struct Process Descriptor mm_struct Memory Descriptor brk mm start_brk end_data BSS Segment start_data Data Segment end_code Text Segment start_code

  30. How Linux Manages Address Space .. Src: [3]

  31. How Linux Manages Address Space .. Example vm_area_struct Src: [3]

  32. How Linux Manages Address Space .. Src: [3]

  33. PAGE-FAULT EXCEPTIONS • Accesses using linear addresses may cause page-fault exceptions. • An access to a linear address may cause a page-fault exception for either of two reasons: • There is no translation for the linear address • There is a translation for the linear address, but its access rights do not permit the access. • In Linux do_page_fault() function is responsible for the handling of page fault.

  34. Page Fault Handling in Linux Overall scheme for the Page Fault handler Src: [2]

  35. PAGE-FAULT EXCEPTIONS The error code that the processor provides on delivery of a page-fault exception Src: [1]

  36. References [1]. Intel 64-ia-32-architectures-software-developer-manual-325462 [2].Understanding the LINUX KERNEL , Third edition, Daniel P. Bovet and Marco Cesati [3]. http://duartes.org/gustavo/blog [4]. YouTube video : Virtual Memory by David Black-Schaffer

  37. THANK YOU

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