1 / 12

Customization Using Variable Instruction Sets

Customization Using Variable Instruction Sets . Krishna V Palem CTO Proceler Inc. Designing Instruction Sets. Choice of instructions is determined by several trade-offs Implementation in a fixed silicon area Ability of the compiler to exploit its presence

ray
Télécharger la présentation

Customization Using Variable Instruction Sets

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Customization Using Variable Instruction Sets Krishna V Palem CTO Proceler Inc.

  2. Designing Instruction Sets • Choice of instructions is determined by several trade-offs • Implementation in a fixed silicon area • Ability of the compiler to exploit its presence • Trade-off between impact on cycle time vs. frequency • Implementation cost is amortized across many applications • Infeasible to tailor support for a small number of low volume applications • Reconfigurable logic enables a new degree of freedom

  3. C P Synthesis Map Place Dynamically Variable Instruction Set Architecture (DVAITA) • Software engineer • C programming • Algorithm Design Off-line Construction Fundamentally alters the hardware/software interface Compiler Fixed ISA DVAITA ISA Application specific Soft Processor Soft Micro-architecture Components Microprocessor core Reconfigurable Logic

  4. DVAITA • DVAITA is a “soft” ISA • Pre-synthesized, pre-placed instruction implementations • DVAITA compiler • Analysis, program transformation, and scheduling algorithms • Compilation to a domain specific ISA • Create a customized micro-architecture at compile time • DVAITA Hardware Support Package • Analogy with Board Support Packages (BSP) • Run-time for host-FPGA communication • Abstraction for linking the supporting hardware/software interfaces

  5. DVAITA Enabled Customization • Customization at the domain level • Soft ISAs for DSP, Telecommunications, Industrial automation and control, etc. • Customization at the program level • Tailored micro-architecture produced at compile time • Customization at the operation level • Tailored arithmetic and logic operations, for example, power vs. speed

  6. Compiling Code Segments to Hardware L1: for (…){ L2: for (…) { .. } .. } … … L3: for (…){ L4: for (…) { L5: for (…) { … } .. } .. } • Datapath • Control • Memory • I/O Interfaces DVAITA ISA • Datapath • Control • Memory • I/O Interfaces DVAITA ISA

  7. Compile-time generation of Application-specific soft processors ISAs can be selected on a domain specific basis

  8. C P Application-Specific Soft Processors Software Engineer • C Programming • Algorithm Design Application-specific soft processors Communication Reconfigurable Computing System (RCS) Compiler Soft Micro- architecture Components Networking Microprocessor core Security Reconfigurable Logic

  9. Commercial Hardware Platforms • High-end System-on-a-Chip solutions • Xilinx Virtex 2 with embedded PPC 405 • Altera Excalibur with embedded ARM • Low-end System-on-a-Chip solutions • Triscend Configurable System on a Chip (CSoC) with embedded ARM • Atmel Field Programmable System Level Integrated Circuits (FPSLIC) with embedded 8-bit custom RISC processor • Board-level products • Mix embedded processors and commercial FPGA solutions

  10. More Generally Architecture Assembly • An ISA view • Synthesis and other hardware design off-line • Much closer to compiler optimizations implies faster compile time Applications Build off-line (synthesis, place and route) Program Prebuilt Implementations “Compiler” selects assembles and optimizes program Data path Storage Interconnect Dynamically variable ISA Architecture implementation Also applicable to yield fixed implementations in silicon

  11. Placing in Perspective

  12. Designed with EDA Tools Software programmable CMP: Custom Microprocessor NP: Network processor The Space for these Technologies ASIC PICO CMP NP Performance COTS PROCESSOR Speed to market

More Related