H. Wieman Sept. 19, 2002 BNL

1. EIC Vertexing for A + A H. Wieman Sept. 19, 2002 BNL

2. Motivation for an inner tracker • A tool for reducing combinatory background to measure yields of particles with short decay times • Works with collections of many events • Background can be less than 1 per event, but signal is still less • Does not extract special decays event by event in the high multiplicity environment of A+A • Measure D mesons

3. Invariant mass reconstruction of D0s k (preliminary simulation) D0 S B M (GeV) Because A+A at RHIC produces very high multiplicity events the vertex detector must be exceptionally good to reduce B Number of events required to get a statistically significant result

4. #1 priority: go thin to reduce Background Shows effects of first layer SI thickness, includes contribution from 760 m beam pipe. Preliminary GEANT simulation B Si thickness reduction 300 m 50 m reduces beam time by factor 19 Si thickness (m)

5. The options • ATLAS style hybrid • Thick ~ 300 m Si • High power 800 W/cm2 – requires liquid cooling, more thickness • CCDs • Very thin • Power vs speed ? • Rad soft • Active Pixel Sensors (APS) • Very thin • Rad hard enough • Slow? But good potential with low power • New technology with normal uncertainties

6. APS Compromises • Short, does not cover diamond • Most running not luminosity limited so not an issue unless run with a very good trigger • Slow, contains multiple events • Background rejection is pileup tolerant

7. tracking in cone of uncertainty SVT real hits pileup hits inner vertex detector pileup causing false rejection primary vertex rejection cut False rejection by pileup • Purpose of vertex detector – remove primary tracks before calculating invariant mass • 40 x design luminosity, 5 ms readout • 400 hits/cm2 • 1.4% pixels filled • false rejection 0.5% • 40 X design luminosity, 20 ms readout • 1500 hits/cm2 • 5.3% pixels filled • false rejection 2.9%

8. A Monolithic Active Pixel Sensor for Charged Particle Tracking and Imaging using Standard VLSI CMOS TechnologyJ.D. Berst, B.Casadei, G.Claus, C.Colledani, W.Dulinski, Y.Hu, D.Husson, J.P.Le Normand, R. Turchetta and J.L.RiesterLEPSI, StrasbourgG.Deptuch, Y.Gornushkin, S.Higueret, M.WinterIReS, Strasbourg • LEPSI - IReS APS • 20 m square pixels • 4 64X64 arrays • MIMOSA 1, 0.6 m CMOS • MIMOSA 2, 0.35 m CMOS

9. All this on a 23 m by 23 m pixel Rapid progress toward fast low power readout with on detector zero suppression

10. LBL APS test with 1.5 GeV/c e-beam 17 e RMS per pixel

11. LBL APS measured MIP signal Sums of 25 pixel regions centered on pixels with ADC  7 Same sums with empty frames Background subtracted APS signal with Bichsel calculation for 8 mm Si • Conclusion, signal to noise is good enough to get good efficiency without excessive false hits • The above analysis is with CDS and leakage current subtraction

12. Active Pixel Sensor (APS) • 20 m square pixels • 5 chips per slat • 90 million pixels • 50 m thick chips • 760 m Be beam pipe 5.6 cm 8 cm

13. One of 8 Modules LBNL mechanical concept for an inner vertex detector for STAR Aluminum/Kapton flex cable under tension 50 m Silicon supported under tension

15. END