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Texas Instruments Incorporated European Customer Training Center University of Applied Sciences Zwickau (FH)

Module 4 : Interrupt System C28x. 32-Bit-Digital Signal Controller TMS320F2812. Texas Instruments Incorporated European Customer Training Center University of Applied Sciences Zwickau (FH). C28x Core Interrupt Lines. 2 non-maskable interrupts (RS, “selectable” NMI)

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Texas Instruments Incorporated European Customer Training Center University of Applied Sciences Zwickau (FH)

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  1. Module 4 : Interrupt System C28x 32-Bit-Digital Signal Controller TMS320F2812 Texas Instruments Incorporated European Customer Training Center University of Applied Sciences Zwickau (FH)

  2. C28x Core Interrupt Lines 2 non-maskable interrupts (RS, “selectable” NMI) 14 maskable interrupts (INT1 – INT14) RS NMI INT1 INT2 INT3 INT4 INT5 C28x CORE INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14

  3. C28x Reset Sources RS pin active C28x Core Watchdog Timer RS To RS pin

  4. Register Bits Initialized at Reset Register bits defined by reset PC 0x3F FFC0 PC loaded with reset vector ACC 0x0000 0000 Accumulator cleared XAR0 - XAR7 0x0000 0000 Auxiliary Registers DP 0x0000 Data Page pointer points to page 0 P 0x0000 0000 P register cleared XT 0x0000 0000 XT register cleared SP 0x0400 Stack Pointer to address 0400 RPC 0x00 0000 Return Program Counter cleared IFR 0x0000 no pending interrupts IER 0x0000 maskable interrupts disabled DBGIER 0x0000 debug interrupts disabled

  5. Control Bits Initialized at Reset Status Register 0 (ST0) SXM = 0 Sign extension off OVM = 0 Overflow mode off TC = 0 test/control flag C = 0 carry bit Z = 0 zero flag N = 0 negative flag V = 0 overflow bit PM = 000 set to left-shift-by-1 OVC = 00 0000 overflow counter Status Register 1 (ST1) INTM = 1 Disable all maskable interrupts - global DBGM = 1 Emulation access/events disabled PAGE0 = 0 Stack addressing mode enabled/Direct addressing disabled VMAP = 1 Interrupt vectors mapped to PM 0x3F FFC0 – 0x3F FFFF SPA = 0 stack pointer even address alignment status bit LOOP = 0 Loop instruction status bit EALLOW = 0 emulation access enable bit IDLESTAT = 0 Idle instruction status bit AMODE = 0 C27x/C28x addressing mode OBJMODE = 0 C27x object mode M0M1MAP = 1 mapping mode bit XF = 0 XF status bit ARP = 0 ARP points to AR0

  6. Reset – Bootloader XMPNMC=1 (microprocessor mode) Reset OBJMODE=0 AMODE=0 ENPIE=0 VMAP=1 M0M1MAP=1 XMPNMC=0 (microcomputer mode) Reset vector fetched from boot ROM 0x3F FFC0 Reset vector fetched from XINTF zone 7 0x3F FFC0 Execution Bootloading Entry Point Routines FLASH SPI H0 SARAM SCI-A OTP Parallel load Boot determined by state of GPIO pins Notes: F2810 XMPNMC tied low internal to device XMPNMC refers to input signal MP/MC is status bit in XINTFCNF2 register XMPNMC only sampled at reset

  7. Bootloader Options GPIO pins F4 F12 F3 F2 1 x x x jump to FLASH address 0x3F 7FF6 * 0 0 1 0 jump to H0 SARAM address 0x3F 8000 * 0 0 0 1 jump to OTP address 0x3D 7800 * 0 1 x x bootload external EEPROM to on-chip memory via SPI port 0 0 1 1 bootload code to on-chip memory via SCI-A port 0 0 0 0 bootload code to on-chip memory via GPIO port B (parallel) * Boot ROM software configures the device for C28x mode before jump

  8. Reset Code Flow - Summary 0x3D 7800 OTP (2K) 0x3D 8000 FLASH (128K) 0x3F 7FF6 0x3F 8000 H0 SARAM (8K) Execution Entry Point Determined By GPIO Pins 0x3F F000 Boot ROM (4K) Boot Code 0x3F FC00     BROM vector (32) 0x3F FFC0 0x3F FC00 RESET Bootloading Routines (SPI, SCI-A, Parallel Load)

  9. Interrupt Sources TINT2 TINT1 TINT0 C28x CORE • RS • NMI • INT1 RS XINT1 INT2 XINT2 INT3 PDPINTx INT12 INT13 INT14 XNMI_XINT13 Internal Sources EV and Non-EV Peripherals (EV, ADC, SPI, SCI, McBSP, CAN) PIE (Peripheral Interrupt Expansion) External Sources

  10. Maskable Interrupt Processing Conceptual Core Overview (IER) “Switch” (INTM) “Global Switch” (IFR) “Latch” Core Interrupt 1 INT1 C28x Core 0 INT2 1 INT14 • A valid signal on a specific interrupt line causes the latch to display a “1” in the appropriate bit • If the individual and global switches are turned “on” the interrupt reaches the core

  11. Interrupt Flag Register (IFR) 11 14 13 12 10 15 9 8 RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9 6 5 4 2 7 1 3 0 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 /*** Manual setting/clearing IFR ***/ extern cregister volatile unsigned int IFR; IFR |= 0x0008; //set INT4 in IFR IFR &= 0xFFF7; //clear INT4 in IFR Pending : IFR Bit = 1 Absent : IFR Bit = 0 • Compiler generates atomic instructions (non-interruptible) for setting/clearing IFR • If interrupt occurs when writing IFR, interrupt has priority • IFR(bit) cleared when interrupt is acknowledged by CPU • Register cleared on reset

  12. Interrupt Enable Register (IER) 11 14 13 12 10 15 9 8 RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9 6 5 4 2 7 1 3 0 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 /*** Interrupt Enable Register ***/ extern cregister volatile unsigned int IER; IER |= 0x0008; //enable INT4 in IER IER &= 0xFFF7; //disable INT4 in IER Enable: Set IER Bit = 1 Disable: Clear IER Bit = 0 • Compiler generates atomic instructions (non-interruptible) for setting/clearing IER • Register cleared on reset

  13. Interrupt Global Mask Bit Bit 0 INTM ST1 /*** Global Interrupts ***/ asm(“ CLRC INTM”); //enable global interrupts asm(“ SETC INTM”); //disable global interrupts • INTM used to globally enable/disable interrupts: • Enable: INTM = 0 • Disable: INTM = 1 (reset value) • INTM modified from assembly code only:

  14. Peripheral Interrupt Expansion - PIE Interrupt Group 1 Peripheral Interrupts 12x8 = 96 PIEIFR1 PIEIER1 PIE module for 96 Interrupts 1 INT1.1 0 INT1.x interrupt group INT1.2 • • INT2.x interrupt group INT1 • • • • INT3.x interrupt group 1 INT4.x interrupt group INT1.8 INT5.x interrupt group 96 INT6.x interrupt group INT7.x interrupt group INT1 – INT 12 INT8.x interrupt group 28x Core Interrupt logic INT9.x interrupt group 12 Interrupts INT10.x interrupt group 28x Core INTM INT11.x interrupt group IER IFR INT12.x interrupt group INT13 (TINT1 / XINT13) INT14 (TINT2) NMI

  15. PIE Registers PIEIFRx register (x = 1 to 12) 15 - 8 7 6 5 4 3 2 1 0 reserved INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 PIEIERx register (x = 1 to 12) 15 - 8 7 6 5 4 3 2 1 0 reserved INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 PIE Interrupt Acknowledge Register (PIEACK) 15 - 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PIEACKx #include “DSP28_Device.h” PieCtrlRegs.PIEIFR1.bit.INTx4 = 1; //manually set IFR for XINT1 in PIE group 1 PieCtrlRegs.PIEIER3.bit.INTx5 = 1; //enable CAPINT1 in PIE group 3 PieCtrlRegs.PIEACK.all = 0x0004; //acknowledge the PIE group 3 PieCtrlRegs.PIECTRL.bit.ENPIE = 1; //enable the PIE PIECTRL register 15 - 1 0 ENPIE PIEVECT

  16. Default Interrupt Vector Table at Reset Prio Vector Offset Reset 00 1 DlogInt RtosInt EmuInt NMI 4 2 3 PIE vector generated by config Tool Used to initialize PIE vectors Illegal User 1-12 - - Default Vector Table Remapped when ENPIE = 1 Int 1 Int 2 Int 3 Int 4 Int 5 Int 6 Int 7 Int 8 Int 9 Int 10 Int 11 Int 12 Int 13 Int 14 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28-3E 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Memory 0 PIE Vectors256 W 0x00 0D00 BROM Vectors64 W 0x3F FFC0 0x3F FFFF

  17. PIE Vector Mapping (ENPIE = 1) Vector name PIE vector address PIE vector Description Not used 0x00 0D00 Reset Vector Never Fetched Here INT1 0x00 0D02 INT1 re-mapped below …… …… …… re-mapped below INT12 0x00 0D18 INT12 re-mapped below INT13 0x00 0D1A XINT1 Interrupt Vector INT14 0x00 0D1C Timer2 – RTOS Vector Datalog 0x00 0D1D Data logging vector …… …… …… USER11 0x00 0D3E User defined TRAP INT1.1 0x00 0D40 PIEINT1.1 interrupt vector …… …… …… INT1.8 0x00 0D4E PIEINT1.8 interrupt vector …… …… …… INT12.1 0x00 0DF0 PIEINT12.1 interrupt vector …… …… …… INT12.8 0x00 0DFE PIEINT12.8 interrupt vector • PIE vector space - 0x00 0D00 – 256 Word memory in Data space • RESET and INT1-INT12 vector locations are Re-mapped • CPU vectors are remapped to 0x00 0D00 in Data space

  18. F2812/10 PIE Interrupt Assignment Table INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 INT1 WAKEINT TINT0 ADCINT XINT2 XINT1 PDPINTB PDPINTA INT2 T1OFINT T1UFINT T1CINT T1PINT CMP3INT CMP2INT CMP1INT INT3 CAPINT3 CAPINT2 CAPINT1 T2OFINT T2UFINT T2CINT T2PINT INT4 T3OFINT T3UFINT T3CINT T3PINT CMP6INT CMP5INT CMP4INT INT5 CAPINT6 CAPINT5 CAPINT4 T4OFINT T4UFINT T4CINT T4PINT INT6 MXINT MRINT SPITXINTA SPIRXINTA INT7 INT8 INT9 SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA ECAN1INT ECAN0INT INT10 INT11 INT12

  19. Device Vector Mapping - Summary MPNMC = 0 (on-chip ROM memory) Reset Vector <0x3F FFCO> = Boot-ROM Code Flash Entry Point <0x3F 7FF6 > = LB _c_int00 User Code Start < _c_int00 > MPNMC = 1 (external memory XINTF) Reset Vector <0x3F FFCO> = _c_int00 User Code Start < _c_int00> Initialization ( ) { EALLOW Load PIE Vectors Enable the PIEIER Enable PIECTRL Enable Core IER Enable INTM EDIS } main() { initialization(); . . . } _c_int00: . . . CALL main() RESET PIE Vector Table 256 Word RAM 0x00 0D00 – 0DFF

  20. Interrupt Response - Hardware Sequence T ST0 AH AL PH PL AR1 AR0 DP ST1 DBSTAT IER PC(msw) PC(lsw) CPU Action Description Registers®stack14 Register words auto saved 0®IFR (bit) Clear corresponding IFR bit 0®IER (bit) Clear corresponding IER bit 1®INTM/DBGM Disable global ints/debug events Vector®PC Loads PC with int vector address Clear other status bitsClear LOOP, EALLOW, IDLESTAT Note: some actions occur simultaneously, none are interruptible

  21. Interrupt Latency 3 1 3 3 4 2 Get vector (3 reg. pairs saved) PF1/PF2/D1 of ISR instruction (3 reg. pairs saved) Save return address D2/R1/R2 of ISR instruction Recognition delay (3) and SP alignment (1) Sync ext. signal (ext. interrupt only) • Minimum latency (to when real work occurs in the ISR): • Internal interrupts: 14 cycles • Maximum latency: Depends on wait states, ready, INTM, etc. Latency Internal interrupt occurs here ext. interrupt occurs here Assumes ISR in internal RAM cycles ISR instruction executed on next cycle Above is for PIE enabled or disabled • External interrupts: 16 cycles

  22. C28x CPU Timers RESET Timer Reload 16 - Bit divide down TDDRH:TDDR 32 - Bit period PRDH:PRD SYSCLKOUT 16 - Bit prescaler PSCH:PSC 32 - Bit counter TIMH:TIM TCR.4 BORROW INT

  23. C28x Timer Interrupt System PIE unit INT1.7 interrupt 28x Core Interrupt logic 28x Core INTM IER IFR TINT0 INT1 INT13 TINT1 / XINT13 INT14 TINT2

  24. C28x Timer Registers Address Register Name 0x0000 0C00 TIMER0TIM Timer 0, Counter Register Low 0x0000 0C01 TIMER0TIMH Timer 0, Counter Register High 0x0000 0C02 TIMER0PRD Timer 0, Period Register Low 0x0000 0C03 TIMER0PRDH Timer 0, Period Register High 0x0000 0C04 TIMER0TCR Timer 0, Control Register 0x0000 0C06 TIMER0TPR Timer 0, Prescaler Register 0x0000 0C07 TIMER0TPRH Timer 0, Prescaler Register High 0x0000 0C08 TIMER1TIM Timer 1, Counter Register Low 0x0000 0C09 TIMER1TIMH Timer 1, Counter Register High 0x0000 0C0A TIMER1PRD Timer 1, Period Register Low 0x0000 0C0B TIMER1PRDH Timer 1, Period Register High 0x0000 0C0C TIMER1TCR Timer 1, Control Register 0x0000 0C0D TIMER1TPR Timer 1, Prescaler Register 0x0000 0C0F TIMER1TPRH Timer 1, Prescaler Register High 0x0000 0C10 to 0C17 Timer 2 Registers ; same layout as above

  25. C28x Timer Control Registers TIMERxTCR Timer Interrupt Flag Write 1 clear bit Timer Interrupt Enable Write 1 to enable INT 15 14 13 12 11 10 9 8 TIF TIE reserved reserved FREE SOFT reserved reserved 7 6 5 4 3 2 1 0 reserved reserved TRB TSS reserved reserved reserved reserved Timer Reload Bit 1 = reload Timer Stop Status 0 = start / 1 = stop Emulator Interaction 1x = run free

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