1 / 9

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design. Jacob Maxa Results of Phase 3: ST65 Netlist 13.12.2012. Institute MD, University of Rostock. Challenge. Create a Verilog netlist for the ST65 technology Build upon NAND/NOR gatter 65 nm structure width

remedios-graves
Télécharger la présentation

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Spezielle Anwendungen des VLSI – EntwurfsApplied VLSI Design Jacob Maxa Results of Phase 3: ST65 Netlist 13.12.2012 Institute MD, University of Rostock

  2. Challenge • Create a Verilog netlist for the ST65 technology • Build upon NAND/NOR gatter • 65 nm structure width • Optimize design for the ST65 technology • Change adder types for 10, 13 and 14 bit width • Carrylookahead • Brent-Kung • Ripple Carry

  3. Calculations Postsynthesis

  4. Calculations Finals Pdyn = 1 µW Pstat = 1 mW area = 3k VDD = 1,0 V

  5. Calculations Finals Pdyn = 1 µW Pstat = 1 mW area = 6k VDD = 1,3 V

  6. Synopsys Flags • Flags • optimize_registers – move registers to decrease the negative slack • set_ungroupyour_filter – unfold the hierarchical structures • set_flatten true -design your_filter -effort high –minimize multiple_output-phase true • set_structure true -design your_filter -boolean true -boolean_effort high -timing true • set_max_area 3000 -ignore_tns • set_max_leakage_power 1 mW • set_max_dynamic_power 1 uW • set_cost_priority {max_delaymin_delaymax_capacitancemax_transitioncell_degradationmax_fanout} • Compiling • compile -map_effort high -power_effort high -ungroup_all -boundary_optimization–scan -auto_ungroupdelay • compile_ultra -incremental -retime

  7. Results (1/2)

  8. Results (2/2)

  9. End • Thanks for your attention! • Questions?

More Related