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Representation of the Hit and its encoding

Representation of the Hit and its encoding.  Sensor is read out in a rolling shutter mode  Rows being selected sequentially by activating a multiplexer every 16 clock cycles. Chip readout architecture including digitalization and zero suppression.

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Representation of the Hit and its encoding

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  1. Representation of the Hit and its encoding Sensor is read out in a rolling shutter mode  Rows being selected sequentially by activating a multiplexer every 16 clock cycles

  2. Chip readout architecture including digitalization and zero suppression Pixel array : 1088 x1088 pixels Readout row by row The row is divided into 17 banks  Analog to digital conversion at the bottom of eachcolumn (Discriminator or ADC)  Zero suppression algorithm : Find N Hits for each group Find M Hits for each row (With N and M determined by pixel array occupancy rate )   Memory wich stores M hits and serial transmission

  3. Adr Decoder Adr 10 bit • Principe of the hit finding algorithm The digital architecture allowing to find the ‘1’s in a row of discriminated outputs is based on a « Priority Look Ahead » (PLA) algorithm  Chain of alternated « NAND » et « NOR » gates for the priority management during the sparse - scan • Fast priority scan path (asynchrone)  CkReadPix  Read hit (address decoded)  RstPix  Desable hit

  4. Block diagram of the Priority Look-Ahead algorithm at the bank level

  5. Hots Pixels ? Without hot pixels management: 25 m : 600 x 32 x 1/(153.10-6)  125 Mbits/s 200ns x 768 = 153 s 18.4 m : 600 x 32 x 1/(204.10-6)  95 Mbits/s 200nsx1024=204,8 s 10-3 • m : 589 pixels => 1189x32 bits increase of 198% • => 1.98 x 125 = 247 Mbits/s 18.4 m : 1114 pixels => 1714 x 32 bits increase of 286% => 2.86 x 95 = 271 Mbits/s 10-4 • m : 59 pixels => 660x32 bits increase of 10% • => 1.1 x 125 ≈ 138 Mbits/s 18.4 m : 111 pixels => 711x32 bits increase of 18.5% => 1.185 x 95 ≈ 113 Mbits/s

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