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Dense-Near/Sparse-Far Hybrid Reconfigurable Neural Network Chip

Dense-Near/Sparse-Far Hybrid Reconfigurable Neural Network Chip. Robin Emery Alex Yakovlev Graeme Chester. Overview. Motivation System Elements & Structure Current Work Future Work. Previous Work. Artificial neural network Xilinx Virtex-II FPGA Variable precision

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Dense-Near/Sparse-Far Hybrid Reconfigurable Neural Network Chip

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  1. Dense-Near/Sparse-FarHybrid ReconfigurableNeural Network Chip Robin Emery Alex Yakovlev Graeme Chester

  2. Overview • Motivation • System Elements & Structure • Current Work • Future Work

  3. Previous Work • Artificial neural network • Xilinx Virtex-II FPGA • Variable precision • Generated using mark-up • Controlled via PC

  4. Previous Work • Exhausted area before routing resource • Synchronous, Low neuron count • No autonomous learning • FPGA routingresources occupy70-90% • Real-time learningawkward

  5. A Neuron

  6. A Network of Neurons • Billions of neurons in the brain • 100 to 3000 connections per neuron • Majority of connections are proximal • Spikes are generally the same

  7. Clusters • Axons of neocortical neurons form connections in clusters

  8. Learning • In the synapse • Plastic connection • Use learning rule • Autonomous insynapse • Wider mechanism mayexist

  9. Motivation • A FPGA-like neural network device would be of interest to neuroscience • Connectivity is also of interest • Observations support a hybrid of local and distal connectivity • More useful with real-time learning

  10. System Elements • Neuron • Synapse • AER Router • AER/Spike Bridge • Routing Resource • Protocol

  11. AER • Address Event Representation • Asynchronous digital multiplexing • Stereotyped digital amplitude events • Nodes share frame of reference • Information is encoded in the time and number of events

  12. Dense-Near Connectivity

  13. Sparse-Far Connectivity

  14. Network Structure

  15. Current Work • Neuron • Configurable threshold • Asynchronous • 7-bit count • Decay • Spike generator

  16. Current Work • Neuron & Spike Generator • 130nm UMC CMOS

  17. Current Work • Software model & protocol refinement • Ongoing work: • Autonomous Synapses • AER Router/Bridges

  18. Evaluation • Topographic map • Compare to popular software modelling tool such as NEURON

  19. Future Work • Long-term learning process • Improve capacity of AER link by grouping spikes • Aggregation of pulse-widths could improve range of dendritic input • Multiplexing of some direct links

  20. Conclusions • Reconfigurable, adaptive neural network system • Real qualities of interest to neuroscientists • Neuron and spike generator manufactured • Interesting avenues for further work

  21. Thank you r.a.emery@ncl.ac.uk

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