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Microarchitecture is Dead

Microarchitecture is Dead. AND We must have a multicore interface that does not require programmers to understand what is going on underneath. What is Microarchitecture?. It is about the implementation It is transparent to the software Ergo, if we really want to protect the programmer

richardsonrobert
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Microarchitecture is Dead

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  1. Microarchitecture is Dead AND We must have a multicore interface that does not require programmers to understand what is going on underneath

  2. What is Microarchitecture? • It is about the implementation • It is transparent to the software • Ergo, if we really want to protect the programmer from seriously understanding the multi-core chip, • Microarchitecture must be very much alive and well

  3. First, a few words about the multi-core chip: The following figure was first published in a UT Tech Report: “ACMP: Balancing Hardware Efficiency and Programmer Efficiency,” TR-HPS-2007-001, Feb, 2007 (Actually, it was first submitted to ISCA in June, 2006, and was rejected  )

  4. The Asymmetric Chip Multiprocessor (ACMP) Large core Largecore Large core Largecore Largecore ACMP Approach “Tile-Large” Approach “Niagara” Approach Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore Niagara-likecore

  5. Large core vs. Small Core LargeCore SmallCore • Out-of-order • Wide fetch e.g. 4-wide • Deeper pipeline • Aggressive branch predictor (e.g. hybrid)‏ • Many functional units • Trace cache • Memory dependence speculation • In-order • Narrow Fetch e.g. 2-wide • Shallow pipeline • Simple branch predictor (e.g. Gshare)‏ • Few functional units

  6. Throughput vs. Serial Performance

  7. To make that chip viable, a lot has to happen: • The interconnect among the cores • The shared resources • Caches (and cache coherence) • Memory Controller(s) • Prefetch mechanisms • Specification of the few heavyweight cores and the many mickey-mouse cores • Performance improvement of the heavyweight core • Specification of accelerators and their interconnect to the cores • Specification of the interface to the software (ISA)

  8. Actually, • I don’t believe the Microarchitecture can do it alone • BUT that does not reduce the importance of the microarchitecture • Everything on the previous slide will be needed • PLUS at least two interfaces: • One for users who can understand the hardware, and • One for the run-time system to smooth the way for users who do not understand the hardware • That will mean breaking the transformation hierarchy

  9. Problem Algorithm Program ISA (Instruction Set Arch) Microarchitecture Circuits Electrons

  10. and that means (in my view) A vibrant future for Microarchitecture

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