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ECE 875: Electronic Devices

This lecture discusses the metal-insulator-semiconductor junction, focusing on the behavior of n-channel and p-channel devices in different substrates. The capacitances and voltage requirements are also explored.

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ECE 875: Electronic Devices

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  1. ECE 875:Electronic Devices Prof. Virginia Ayres Electrical & Computer Engineering Michigan State University ayresv@msu.edu

  2. Lecture 29, 24 Mar 14 • Chp 04: metal-insulator-semiconductor junction: GATES • Q, E , V/y: WD , Vi • Capacitances VM Ayres, ECE875, S14

  3. Lec 26: p-type Si Use energy band diagram to find: Electron concentration in channel V requirements: battery = $ E –field/Vi across the insulator: breakdown not good VM Ayres, ECE875, S14

  4. 2 Or nn0 Or nn0 Or pp0/nn0 3: @ ys for known condition 1. Know substrate doping NA or ND VM Ayres, ECE875, S14

  5. From Lec 26-27 example: Known condition: n-channel in p-substrate: VM Ayres, ECE875, S14

  6. From Lec 27 example: Known condition: p-channel in n-substrate:

  7. Have: values for ys and Qs : Therefore have potential drop across the dielectric: Vi = |Qs| d ei Makes sense to evaluate this in strong inversion/accumulation Therefore have battery V

  8. Example: is this an n-channel or p-channel device?

  9. Answer: is this an n-channel in p-substrate (NA)

  10. Lec 26: p-type Si Use energy band diagram to find: Electron concentration in channel V requirements: battery = $ E –field/Vi across the insulator: breakdown not good VM Ayres, ECE875, S14

  11. Qs = Qn + Qdepletion = Qn + q (NA or ND) WD

  12. Qs = Qn + Qdepletion = Qn + q (NA or ND) WD

  13. Lecture 29, 24 Mar 14 • Chp 04: metal-insulator-semiconductor junction: GATES • Q, E , V/y: WD , Vi • Capacitances VM Ayres, ECE875, S14

  14. ON to OFF: n-channel in a p-substrate: VM Ayres, ECE875, S14

  15. OFF to ON: n-channel in a p-substrate: ON: Strong inversion Going OFF: intrinsic OFF: Strong accumulation Going OFF: Flatband VM Ayres, ECE875, S14

  16. Fig 07: n-channel in p-substrate: ON OFF C / Ci VM Ayres, ECE875, S14

  17. Fig. 07 shows all behaviors. Complication: C-V curves depend on frequency of voltage sweep. Gate voltage: Sweeping Vgate for example ± 4 Volts over and over to turn the channel OFF and ON: binary logic Low: 1- 1 kHz Intermediate: 1 kHz - 1 MHz High: > 1 MHz VM Ayres, ECE875, S14

  18. Start: Low frequency C-V curves VM Ayres, ECE875, S14

  19. Example: what values are easiest to determine experimentally? VM Ayres, ECE875, S14

  20. Answer: @OFF, @ON and minimum Example: Why so? Answer: compare to slide 18, works for now VM Ayres, ECE875, S14

  21. Note that Qn can be big number Units = C/cm2 E (x) = constant || plate capacitor Ci E (x) = distributed capacitor CD = dQs/dys Total C: Ci and CD are in series VM Ayres, ECE875, S14

  22. VM Ayres, ECE875, S14

  23. CD = dQs/dys = large neglect C ≈ Ci Also true in strong inversion VM Ayres, ECE875, S14

  24. Can normalize curve to Ci I will continue with experimental readings in F/cm2. Fancy C means Farads/Area. OFF ON 1.0 C / Ci VM Ayres, ECE875, S14

  25. OFF ON 2.0 1.73 1.0 C (x 10-7 F/cm2) 0.5 C-V curve for an n-channel in a p-type Si block Low frequency curve: 1 Hz Ci= eie0 d Units: F/cm2 VM Ayres, ECE875, S14

  26. Important: Use C-V reading to experimentally solve for the gate oxide thickness d: Ci= eie0 => d = eie0 dCi OFF ON 2.0 1.73 1.0 C (x 10-7 F/cm2) 0.5 C-V curve for an n-channel in a p-type Si block Low frequency curve: 1 Hz VM Ayres, ECE875, S14

  27. Next: Cmin is easy to identify on the experimental curve: VM Ayres, ECE875, S14

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